From patchwork Sat Apr 28 01:58:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Xiong" X-Patchwork-Id: 155619 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E8817B6FD0 for ; Sat, 28 Apr 2012 11:59:48 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758878Ab2D1B7T (ORCPT ); Fri, 27 Apr 2012 21:59:19 -0400 Received: from wolverine01.qualcomm.com ([199.106.114.254]:34550 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758833Ab2D1B7L (ORCPT ); Fri, 27 Apr 2012 21:59:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qca.qualcomm.com; i=xiong@qca.qualcomm.com; q=dns/txt; s=qcdkim; t=1335578351; x=1367114351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=U8A3uB3dAn2JMYBzuHK1+mmJZon7Tly5TCnZK32Ku2E=; b=gtFzML0cpIwRoFdOTRWQmZ0/SKtZPwiFcy1GpZKgEtJIGD0dno3Z4QCM bCuvpuzJU21Y9a39XD+vgDY1X2JEjSZUNep3FuCMVdfrwkcnOJw+fxB7O jfXtsZBCPlJJaKjdvi9whrFxr+sadGm+Dgaw9eFPEEiR/dzjvCkpFeZ99 c=; X-IronPort-AV: E=McAfee;i="5400,1158,6694"; a="185773424" Received: from ironmsg03-r.qualcomm.com ([172.30.46.17]) by wolverine01.qualcomm.com with ESMTP; 27 Apr 2012 18:59:11 -0700 X-IronPort-AV: E=Sophos;i="4.75,491,1330934400"; d="scan'208";a="242469479" Received: from nasanexhc05.na.qualcomm.com ([172.30.48.2]) by Ironmsg03-R.qualcomm.com with ESMTP/TLS/RC4-SHA; 27 Apr 2012 18:59:11 -0700 Received: from qcmail1.qualcomm.com (172.30.48.1) by qcmail1.qualcomm.com (172.30.48.2) with Microsoft SMTP Server (TLS) id 14.2.283.3; Fri, 27 Apr 2012 18:59:09 -0700 Received: by qcmail1.qualcomm.com (sSMTP sendmail emulation); Sat, 28 Apr 2012 09:59:06 +0800 From: xiong To: , , CC: , , xiong Subject: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt Date: Sat, 28 Apr 2012 09:58:36 +0800 Message-ID: <1335578325-21326-2-git-send-email-xiong@qca.qualcomm.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1335578325-21326-1-git-send-email-xiong@qca.qualcomm.com> References: <1335578325-21326-1-git-send-email-xiong@qca.qualcomm.com> MIME-Version: 1.0 X-Originating-IP: [172.30.48.1] Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org All supported devices have one issue that msi interrupt doesn't assert if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set. Add workaround in drivers/pci/quirks.c Signed-off-by: xiong --- drivers/pci/quirks.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4bf7102..953ec3f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2626,6 +2626,18 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, + quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, + quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, + quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, + quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, + quirk_msi_intx_disable_bug); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, + quirk_msi_intx_disable_bug); #endif /* CONFIG_PCI_MSI */ /* Allow manual resource allocation for PCI hotplug bridges