From patchwork Tue Aug 9 09:16:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamie Iles X-Patchwork-Id: 109182 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 56431B6F7B for ; Tue, 9 Aug 2011 19:18:25 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752982Ab1HIJSQ (ORCPT ); Tue, 9 Aug 2011 05:18:16 -0400 Received: from mail-wy0-f174.google.com ([74.125.82.174]:54522 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752745Ab1HIJSP (ORCPT ); Tue, 9 Aug 2011 05:18:15 -0400 Received: by mail-wy0-f174.google.com with SMTP id 24so212672wyg.19 for ; Tue, 09 Aug 2011 02:18:14 -0700 (PDT) Received: by 10.227.38.164 with SMTP id b36mr5677657wbe.54.1312881494416; Tue, 09 Aug 2011 02:18:14 -0700 (PDT) Received: from localhost (cpc3-chap8-2-0-cust205.aztw.cable.virginmedia.com [94.171.253.206]) by mx.google.com with ESMTPS id ej15sm3845015wbb.14.2011.08.09.02.18.12 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 09 Aug 2011 02:18:13 -0700 (PDT) From: Jamie Iles To: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: plagnioj@jcrosoft.com, Jamie Iles Subject: [PATCHv3 8/9] macb: support DMA bus widths > 32 bits Date: Tue, 9 Aug 2011 10:16:50 +0100 Message-Id: <1312881411-2376-9-git-send-email-jamie@jamieiles.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1312881411-2376-1-git-send-email-jamie@jamieiles.com> References: <1312881411-2376-1-git-send-email-jamie@jamieiles.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some GEM implementations may support DMA bus widths up to 128 bits. We can get the maximum supported DMA bus width from the design configuration register so use that to program the device up. Signed-off-by: Jamie Iles Acked-by: David S. Miller Acked-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD --- drivers/net/macb.c | 23 +++++++++++++++++++++++ drivers/net/macb.h | 19 +++++++++++++++++++ 2 files changed, 42 insertions(+), 0 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0e35804..a8a9b4b 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -836,6 +836,27 @@ static u32 macb_mdc_clk_div(struct macb *bp) return config; } +/* + * Get the DMA bus width field of the network configuration register that we + * should program. We find the width from decoding the design configuration + * register to find the maximum supported data bus width. + */ +static u32 macb_dbw(struct macb *bp) +{ + if (!macb_is_gem(bp)) + return 0; + + switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { + case 4: + return GEM_BF(DBW, GEM_DBW128); + case 2: + return GEM_BF(DBW, GEM_DBW64); + case 1: + default: + return GEM_BF(DBW, GEM_DBW32); + } +} + static void macb_init_hw(struct macb *bp) { u32 config; @@ -851,6 +872,7 @@ static void macb_init_hw(struct macb *bp) config |= MACB_BIT(CAF); /* Copy All Frames */ if (!(bp->dev->flags & IFF_BROADCAST)) config |= MACB_BIT(NBC); /* No BroadCast */ + config |= macb_dbw(bp); macb_writel(bp, NCFGR, config); /* Initialize TX and RX buffers */ @@ -1277,6 +1299,7 @@ static int __init macb_probe(struct platform_device *pdev) /* Set MII management clock divider */ config = macb_mdc_clk_div(bp); + config |= macb_dbw(bp); macb_writel(bp, NCFGR, config); macb_get_hwaddr(bp); diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 1367b92..71424aa 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -69,6 +69,13 @@ #define GEM_SA1B 0x0088 #define GEM_SA1T 0x008C #define GEM_OTX 0x0100 +#define GEM_DCFG1 0x0280 +#define GEM_DCFG2 0x0284 +#define GEM_DCFG3 0x0288 +#define GEM_DCFG4 0x028c +#define GEM_DCFG5 0x0290 +#define GEM_DCFG6 0x0294 +#define GEM_DCFG7 0x0298 /* Bitfields in NCR */ #define MACB_LB_OFFSET 0 @@ -139,6 +146,14 @@ /* GEM specific NCFGR bitfields. */ #define GEM_CLK_OFFSET 18 #define GEM_CLK_SIZE 3 +#define GEM_DBW_OFFSET 21 +#define GEM_DBW_SIZE 2 + +/* Constants for data bus width. */ +#define GEM_DBW32 0 +#define GEM_DBW64 1 +#define GEM_DBW128 2 + /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 #define MACB_NSR_LINK_SIZE 1 @@ -247,6 +262,10 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfields in DCFG1. */ +#define GEM_DBWDEF_OFFSET 25 +#define GEM_DBWDEF_SIZE 3 + /* Constants for CLK */ #define MACB_CLK_DIV8 0 #define MACB_CLK_DIV16 1