From patchwork Mon Jun 20 00:58:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kirsher, Jeffrey T" X-Patchwork-Id: 101015 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E730DB7010 for ; Mon, 20 Jun 2011 10:59:19 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751466Ab1FTA67 (ORCPT ); Sun, 19 Jun 2011 20:58:59 -0400 Received: from mga09.intel.com ([134.134.136.24]:10991 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751222Ab1FTA67 (ORCPT ); Sun, 19 Jun 2011 20:58:59 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 19 Jun 2011 17:58:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.65,390,1304319600"; d="scan'208";a="16971446" Received: from unknown (HELO jtkirshe-mobl.amr.corp.intel.com) ([10.255.12.216]) by orsmga001.jf.intel.com with ESMTP; 19 Jun 2011 17:58:44 -0700 From: Jeff Kirsher To: davem@davemloft.net Cc: John Fastabend , netdev@vger.kernel.org, gospo@redhat.com, Jeff Kirsher Subject: [net-next 08/17] ixgbe: consolidate MRQC and MTQC handling Date: Sun, 19 Jun 2011 17:58:29 -0700 Message-Id: <1308531518-17298-9-git-send-email-jeffrey.t.kirsher@intel.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1308531518-17298-1-git-send-email-jeffrey.t.kirsher@intel.com> References: <1308531518-17298-1-git-send-email-jeffrey.t.kirsher@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: John Fastabend The MRQC and MTQC registers are configured in the main setup path but are also reconfigured in the DCB setup path. The DCB path fixes the DCB configuration by configuring the SECTXMINIFG gap which is required for DCB pause to operate correctly. This patch reduces the duplicate code and does all setup in ixgbe_setup_mtqc() and ixgbe_setup_mrqc(). Additionally, this removes the IXGBE_QDE. This write never set the WRITE bit in the register so the write was not actually doing anything. Also this was to clear the register but, it is never set and defaults to zero. If this is needed for SRIOV it should be added correctly in a follow up patch. But it's never been working so removing it here should be OK. Signed-off-by: John Fastabend Tested-by: Ross Brattain Signed-off-by: Jeff Kirsher --- drivers/net/ixgbe/ixgbe_dcb_82599.c | 57 ----------------------------------- drivers/net/ixgbe/ixgbe_main.c | 7 ++++ 2 files changed, 7 insertions(+), 57 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c index befe8ad..ade9820 100644 --- a/drivers/net/ixgbe/ixgbe_dcb_82599.c +++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c @@ -319,62 +319,6 @@ static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) } /** - * ixgbe_dcb_config_82599 - Configure general DCB parameters - * @hw: pointer to hardware structure - * - * Configure general DCB parameters. - */ -static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw) -{ - u32 reg; - u32 q; - - /* Disable the Tx desc arbiter so that MTQC can be changed */ - reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); - reg |= IXGBE_RTTDCS_ARBDIS; - IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); - - /* Enable DCB for Rx with 8 TCs */ - reg = IXGBE_READ_REG(hw, IXGBE_MRQC); - switch (reg & IXGBE_MRQC_MRQE_MASK) { - case 0: - case IXGBE_MRQC_RT4TCEN: - /* RSS disabled cases */ - reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; - break; - case IXGBE_MRQC_RSSEN: - case IXGBE_MRQC_RTRSS4TCEN: - /* RSS enabled cases */ - reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN; - break; - default: - /* Unsupported value, assume stale data, overwrite no RSS */ - reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; - } - IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg); - - /* Enable DCB for Tx with 8 TCs */ - reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; - IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); - - /* Disable drop for all queues */ - for (q = 0; q < 128; q++) - IXGBE_WRITE_REG(hw, IXGBE_QDE, q << IXGBE_QDE_IDX_SHIFT); - - /* Enable the Tx desc arbiter */ - reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); - reg &= ~IXGBE_RTTDCS_ARBDIS; - IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); - - /* Enable Security TX Buffer IFG for DCB */ - reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); - reg |= IXGBE_SECTX_DCB; - IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); - - return 0; -} - -/** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @refill: refill credits index by traffic class @@ -388,7 +332,6 @@ static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw) s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) { - ixgbe_dcb_config_82599(hw); ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type, prio_tc); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index fba1e323..20467da 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -2816,6 +2816,7 @@ static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) struct ixgbe_hw *hw = &adapter->hw; u32 rttdcs; u32 mask; + u32 reg; if (hw->mac.type == ixgbe_mac_82598EB) return; @@ -2838,6 +2839,12 @@ static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) /* We enable 8 traffic classes, DCB only */ IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); + + /* Enable Security TX Buffer IFG for DCB */ + reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); + reg |= IXGBE_SECTX_DCB; + IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); + break; default: