From patchwork Mon Apr 12 16:58:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Carlson X-Patchwork-Id: 49981 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DDE9DB7C8E for ; Tue, 13 Apr 2010 02:59:00 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753108Ab0DLQ6v (ORCPT ); Mon, 12 Apr 2010 12:58:51 -0400 Received: from mms1.broadcom.com ([216.31.210.17]:4896 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752424Ab0DLQ6u (ORCPT ); Mon, 12 Apr 2010 12:58:50 -0400 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Mon, 12 Apr 2010 09:58:38 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-12.broadcom.com (10.11.16.101) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 12 Apr 2010 10:00:02 -0700 Received: from xw6200 (mcarlson.broadcom.com [10.12.148.101]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id 7DF8269CAD; Mon, 12 Apr 2010 09:58:37 -0700 (PDT) From: "Matt Carlson" To: davem@davemloft.net cc: netdev@vger.kernel.org, andy@greyhouse.net, mcarlson@broadcom.com Subject: [PATCH net-next 3/8] tg3: Reduce 57765 core clock when link at 10Mbps Date: Mon, 12 Apr 2010 09:58:26 -0700 Message-ID: <1271091511-11173-4-git-send-email-mcarlson@broadcom.com> X-Mailer: git-send-email 1.6.4.4 MIME-Version: 1.0 X-WSS-ID: 67DD8EB420S87209957-01-01 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch reduces the core clock to 6.25MHz when operating at 10Mbps link speed. This is needed to prevent a bug that will ultimately cause transmits to cease. Signed-off-by: Matt Carlson Reviewed-by: Michael Chan --- drivers/net/tg3.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a0ab89e..3e89323 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); tw32(GRC_MODE, grc_mode); + + val = tr32(TG3_CPMU_LSPD_10MB_CLK); + val &= ~CPMU_LSPD_10MB_MACCLK_MASK; + val |= CPMU_LSPD_10MB_MACCLK_6_25; + tw32(TG3_CPMU_LSPD_10MB_CLK, val); } /* This works around an issue with Athlon chipsets on