From patchwork Wed Apr 8 08:50:48 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhananjay Phadke X-Patchwork-Id: 25721 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 2E78DDDD0B for ; Wed, 8 Apr 2009 18:53:11 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762788AbZDHIvm (ORCPT ); Wed, 8 Apr 2009 04:51:42 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1761269AbZDHIvi (ORCPT ); Wed, 8 Apr 2009 04:51:38 -0400 Received: from nxgate.netxen.com ([38.99.60.130]:49854 "EHLO unm84.unmin.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758786AbZDHIvG (ORCPT ); Wed, 8 Apr 2009 04:51:06 -0400 Received: by unm84.unmin.com (Postfix, from userid 720) id A6288E92E6; Wed, 8 Apr 2009 01:50:49 -0700 (PDT) From: Dhananjay Phadke To: netdev@vger.kernel.org Cc: davem@davemloft.net Subject: [patch next 11/11] netxen: cache align register map table Date: Wed, 8 Apr 2009 01:50:48 -0700 Message-Id: <1239180648-29842-12-git-send-email-dhananjay@netxen.com> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1239180648-29842-1-git-send-email-dhananjay@netxen.com> References: <1239180648-29842-1-git-send-email-dhananjay@netxen.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Aligning register offset translation table imporves performance on rx side. Signed-off-by: Dhananjay Phadke --- drivers/net/netxen/netxen_nic_hw.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 9439f89..3bb2b8c 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c @@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter, } #define CRB_WIN_LOCK_TIMEOUT 100000000 -static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { +static crb_128M_2M_block_map_t +crb_128M_2M_map[64] __cacheline_aligned_in_smp = { {{{0, 0, 0, 0} } }, /* 0: PCI */ {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ {1, 0x0110000, 0x0120000, 0x130000},