From patchwork Fri Jul 21 11:25:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 792077 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xDTfr169rz9ryv for ; Fri, 21 Jul 2017 21:53:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752275AbdGULxG convert rfc822-to-8bit (ORCPT ); Fri, 21 Jul 2017 07:53:06 -0400 Received: from us-smtp-delivery-107.mimecast.com ([216.205.24.107]:42736 "EHLO us-smtp-delivery-107.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752048AbdGULxF (ORCPT ); Fri, 21 Jul 2017 07:53:05 -0400 Received: from CPH-EX1.SDESIGNS.COM (195-215-56-170-static.dk.customer.tdc.net [195.215.56.170]) (Using TLS) by us-smtp-1.mimecast.com with ESMTP id us-mta-59-GnmXrykeOO-S5TJ_9IW54g-1; Fri, 21 Jul 2017 07:53:03 -0400 Received: from [172.27.0.114] (172.27.0.114) by CPH-EX1.sdesigns.com (192.168.10.36) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 21 Jul 2017 13:52:59 +0200 Subject: [PATCH v2 1/4] net: phy: at803x: Document RGMII RX and TX clock delay issues From: Marc Gonzalez To: Florian Fainelli , Andrew Lunn , Mans Rullgard , Martin Blumenstingl , Grygorii Strashko , Fabio Estevam , Zefir Kurtisi , Timur Tabi , Daniel Mack CC: netdev , Linux ARM , "David S. Miller" , Thibaud Cornic , Mason References: <2617d673-ef81-5e7f-4730-ed3aa3f1c2c6@sigmadesigns.com> Message-ID: <051653a2-946f-6a0b-4cff-b403d1197038@sigmadesigns.com> Date: Fri, 21 Jul 2017 13:25:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Firefox/52.0 SeaMonkey/2.49.1 MIME-Version: 1.0 In-Reply-To: <2617d673-ef81-5e7f-4730-ed3aa3f1c2c6@sigmadesigns.com> X-Originating-IP: [172.27.0.114] X-MC-Unique: GnmXrykeOO-S5TJ_9IW54g-1 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The current code supports enabling RGMII RX and TX clock delays. The unstated assumption is that these settings are disabled by default at reset, which is not the case. RX clock delay is enabled at reset. And TX clock delay "survives" across SW resets. Thus, if the bootloader enables TX clock delay, it will remain enabled at reset in Linux. Signed-off-by: Marc Gonzalez --- drivers/net/phy/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c1e52b9dc58d..7a0954513b91 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -283,6 +283,12 @@ static int at803x_config_init(struct phy_device *phydev) if (ret < 0) return ret; + /* + * NB: This code assumes that RGMII RX clock delay is disabled + * at reset, but actually, RX clock delay is enabled at reset. + * Disabling the delay if it has not been explicitly requested + * breaks boards that rely on the enabled-by-default behavior. + */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { ret = at803x_enable_rx_delay(phydev); @@ -290,6 +296,12 @@ static int at803x_config_init(struct phy_device *phydev) return ret; } + /* + * NB: This code assumes that RGMII TX clock delay is disabled + * at reset, but actually, TX clock delay "survives" across SW + * resets. If the bootloader enables TX clock delay, Linux is + * stuck with that setting. + */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { ret = at803x_enable_tx_delay(phydev);