diff mbox series

[20/30] at_hdmac.c: Quite a few spello fixes

Message ID d4e6597ed691d7faf4b35ca75e392706bdb16d1d.1616971780.git.unixbhaskar@gmail.com (mailing list archive)
State Not Applicable
Headers show
Series DMA: Mundane typo fixes | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch powerpc/merge (87d76f542a24ecfa797e9bd3bb56c0f19aabff57)
snowpatch_ozlabs/checkpatch warning total: 0 errors, 1 warnings, 0 checks, 53 lines checked
snowpatch_ozlabs/needsstable success Patch has no Fixes tags

Commit Message

Bhaskar Chowdhury March 28, 2021, 11:53 p.m. UTC 
s/tranfers/transfers/
s/maxium/maximum/
s/previouly/previously/
s/broked/broken/
s/embedds/embeds/ .... three different places.

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
 drivers/dma/at_hdmac.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

--
2.26.3
diff mbox series

Patch

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 30ae36124b1d..02c09532a9e4 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -374,11 +374,11 @@  static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
 		 * a second time. If the two consecutive read values of the DSCR
 		 * are the same then we assume both refers to the very same
 		 * child descriptor as well as the CTRLA value read inbetween
-		 * does. For cyclic tranfers, the assumption is that a full loop
+		 * does. For cyclic transfers, the assumption is that a full loop
 		 * is "not so fast".
 		 * If the two DSCR values are different, we read again the CTRLA
 		 * then the DSCR till two consecutive read values from DSCR are
-		 * equal or till the maxium trials is reach.
+		 * equal or till the maximum trials is reach.
 		 * This algorithm is very unlikely not to find a stable value for
 		 * DSCR.
 		 */
@@ -403,7 +403,7 @@  static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)

 			/*
 			 * DSCR has changed inside the DMA controller, so the
-			 * previouly read value of CTRLA may refer to an already
+			 * previously read value of CTRLA may refer to an already
 			 * processed descriptor hence could be outdated.
 			 * We need to update ctrla to match the current
 			 * descriptor.
@@ -564,7 +564,7 @@  static void atc_handle_error(struct at_dma_chan *atchan)
 	spin_lock_irqsave(&atchan->lock, flags);
 	/*
 	 * The descriptor currently at the head of the active list is
-	 * broked. Since we don't have any way to report errors, we'll
+	 * broken. Since we don't have any way to report errors, we'll
 	 * just have to scream loudly and try to carry on.
 	 */
 	bad_desc = atc_first_active(atchan);
@@ -870,7 +870,7 @@  atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 		atc_desc_chain(&first, &prev, desc);
 	}

-	/* First descriptor of the chain embedds additional information */
+	/* First descriptor of the chain embeds additional information */
 	first->txd.cookie = -EBUSY;
 	first->total_len = len;

@@ -1199,7 +1199,7 @@  atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	/* set end-of-link to the last link descriptor of list*/
 	set_desc_eol(prev);

-	/* First descriptor of the chain embedds additional information */
+	/* First descriptor of the chain embeds additional information */
 	first->txd.cookie = -EBUSY;
 	first->total_len = total_len;

@@ -1358,7 +1358,7 @@  atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 	/* lets make a cyclic list */
 	prev->lli.dscr = first->txd.phys;

-	/* First descriptor of the chain embedds additional information */
+	/* First descriptor of the chain embeds additional information */
 	first->txd.cookie = -EBUSY;
 	first->total_len = buf_len;