From patchwork Thu Jul 30 22:42:39 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Mason X-Patchwork-Id: 30406 Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 8846BB7BD9 for ; Fri, 31 Jul 2009 08:43:06 +1000 (EST) Received: by ozlabs.org (Postfix) id 64203DDDB2; Fri, 31 Jul 2009 08:43:06 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 62AB6DDD1B for ; Fri, 31 Jul 2009 08:43:06 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id E458EB7EF5 for ; Fri, 31 Jul 2009 08:42:52 +1000 (EST) Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 7C302B7BD9 for ; Fri, 31 Jul 2009 08:42:45 +1000 (EST) Received: by ozlabs.org (Postfix) id 6225BDDDB2; Fri, 31 Jul 2009 08:42:45 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e33.co.us.ibm.com", Issuer "Equifax" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 050C0DDDA2 for ; Fri, 31 Jul 2009 08:42:44 +1000 (EST) Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by e33.co.us.ibm.com (8.14.3/8.13.1) with ESMTP id n6UMers6009603 for ; Thu, 30 Jul 2009 16:40:53 -0600 Received: from d03av04.boulder.ibm.com (d03av04.boulder.ibm.com [9.17.195.170]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id n6UMgf1h197630 for ; Thu, 30 Jul 2009 16:42:41 -0600 Received: from d03av04.boulder.ibm.com (loopback [127.0.0.1]) by d03av04.boulder.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n6UMgfGB006668 for ; Thu, 30 Jul 2009 16:42:41 -0600 Received: from [127.0.0.1] (sig-9-49-133-88.mts.ibm.com [9.49.133.88]) by d03av04.boulder.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id n6UMgdKV006609; Thu, 30 Jul 2009 16:42:40 -0600 Message-ID: <4A7221DF.5040402@us.ibm.com> Date: Thu, 30 Jul 2009 15:42:39 -0700 From: Mike Mason User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) MIME-Version: 1.0 To: linuxppc-dev@ozlabs.org, linux-pci@vger.kernel.org, linasvepstas@gmail.com, benh@kernel.crashing.org, Paul Mackerras Subject: [PATCH 3/3] Support for PCI Express reset type References: <4A722121.4010307@us.ibm.com> In-Reply-To: <4A722121.4010307@us.ibm.com> Cc: Richard Lary X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This is the third of three patches that implement a bit field that PCI Express device drivers can use to indicate they need a fundamental reset during error recovery. By default, the EEH framework on powerpc does what's known as a "hot reset" during recovery of a PCI Express device. We've found a case where the device needs a "fundamental reset" to recover properly. The current PCI error recovery and EEH frameworks do not support this distinction. The attached patch makes changes to EEH to utilize the new bit field. These patches supersede the previously submitted patch that implemented a fundamental reset bit field. Please review and let me know of any concerns. Signed-off-by: Mike Mason Signed-off-by: Richard Lary Signed-off-by: Linas Vepstas diff -uNrp a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c --- a/arch/powerpc/kernel/pci_64.c 2009-07-13 14:25:24.000000000 -0700 +++ b/arch/powerpc/kernel/pci_64.c 2009-07-15 10:26:26.000000000 -0700 @@ -143,6 +143,7 @@ struct pci_dev *of_create_pci_dev(struct dev->dev.bus = &pci_bus_type; dev->devfn = devfn; dev->multifunction = 0; /* maybe a lie? */ + dev->needs_freset = 0; /* pcie fundamental reset required */ dev->vendor = get_int_prop(node, "vendor-id", 0xffff); dev->device = get_int_prop(node, "device-id", 0xffff); diff -uNrp a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c --- a/arch/powerpc/platforms/pseries/eeh.c 2009-06-09 20:05:27.000000000 -0700 +++ b/arch/powerpc/platforms/pseries/eeh.c 2009-07-15 10:29:04.000000000 -0700 @@ -744,7 +744,15 @@ int pcibios_set_pcie_reset_state(struct static void __rtas_set_slot_reset(struct pci_dn *pdn) { - rtas_pci_slot_reset (pdn, 1); + struct pci_dev *dev = pdn->pcidev; + + /* Determine type of EEH reset required by device, + * default hot reset or fundamental reset + */ + if (dev->needs_freset) + rtas_pci_slot_reset(pdn, 3); + else + rtas_pci_slot_reset(pdn, 1); /* The PCI bus requires that the reset be held high for at least * a 100 milliseconds. We wait a bit longer 'just in case'. */