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[217.248.130.6]) by smtp.googlemail.com with ESMTPSA id 131sm15867486wmu.17.2016.05.07.15.54.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 07 May 2016 15:54:45 -0700 (PDT) Received: from localhost.daheim ([127.0.0.1] helo=debian64.localnet) by debian64.daheim with esmtps (TLS1.0:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.87) (envelope-from ) id 1azB7U-0003hi-Ia; Sun, 08 May 2016 00:54:44 +0200 To: linux-usb@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: usb: dwc2: regression on MyBook Live Duo / Canyonlands since 4.3.0-rc4 Date: Sun, 08 May 2016 00:54:44 +0200 Message-ID: <4231696.iL6nGs74X8@debian64> User-Agent: KMail/4.14.10 (Linux/4.6.0-rc5-wt; KDE/4.14.14; x86_64; ; ) MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Christian Lamparter via Linuxppc-dev Reply-To: Christian Lamparter Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hello, I've been looking in getting the MyBook Live Duo's USB OTG port to function. The SoC is a APM82181. Which has a PowerPC 464 core and related to the supported canyonlands architecture in arch/powerpc/. Currently in -next the dwc2 module doesn't load: dwc2 4bff80000.usbotg: dwc2_core_reset() HANG! AHB Idle GRSTCTL=80 dwc2 4bff80000.usbotg: Bad value for GSNPSID: 0x0a29544f Looking at the Bad GSNPSID value: 0x0a29544f. It is obvious that this is an endian problem. git finds this patch: commit 95c8bc3609440af5e4a4f760b8680caea7424396 Author: Antti Seppälä Date: Thu Aug 20 21:41:07 2015 +0300 usb: dwc2: Use platform endianness when accessing registers This patch is necessary to access dwc2 registers correctly on big-endian systems such as the mips based SoCs made by Lantiq. Then dwc2 can be used to replace ifx-hcd driver for Lantiq platforms found e.g. in OpenWrt. The patch was autogenerated with the following commands: $EDITOR core.h sed -i "s/\/dwc2_readl/g" *.c hcd.h hw.h sed -i "s/\/dwc2_writel/g" *.c hcd.h hw.h Some files were then hand-edited to fix checkpatch.pl warnings about too long lines. which unfortunately, broke the USB-OTG port on the MyBook Live Duo. Reverting to the readl / writel: --- diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 3c58d63..c021c1f 100644 --- restores the dwc-otg port to full working order: dwc2 4bff80000.usbotg: Specified GNPTXFDEP=1024 > 256 dwc2 4bff80000.usbotg: EPs: 3, shared fifos, 2042 entries in SPRAM dwc2 4bff80000.usbotg: DWC OTG Controller dwc2 4bff80000.usbotg: new USB bus registered, assigned bus number 1 dwc2 4bff80000.usbotg: irq 33, io mem 0x00000000 hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected root@mbl:~# usb 1-1: new high-speed USB device number 2 using dwc2 So, what to do? Regards, Christian --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -66,7 +66,7 @@ static inline u32 dwc2_readl(const void __iomem *addr) { - u32 value = __raw_readl(addr); + u32 value = readl(addr); /* In order to preserve endianness __raw_* operation is used. Therefore * a barrier is needed to ensure IO access is not re-ordered across @@ -78,7 +78,7 @@ static inline u32 dwc2_readl(const void __iomem *addr) static inline void dwc2_writel(u32 value, void __iomem *addr) { - __raw_writel(value, addr); + writel(value, addr); /* * In order to preserve endianness __raw_* operation is used. Therefore