From patchwork Wed Jun 12 08:19:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rojhalat Ibrahim X-Patchwork-Id: 250711 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id BF9C92C00AC for ; Wed, 12 Jun 2013 18:20:06 +1000 (EST) Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 95B4F2C0079 for ; Wed, 12 Jun 2013 18:19:38 +1000 (EST) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3bVgwg19tpz3hhcW; Wed, 12 Jun 2013 10:19:30 +0200 (CEST) Received: from mail.dmz.schenk (host-82-135-47-202.customer.m-online.net [82.135.47.202]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPS id 3bVgwf5Tl2zbbfS; Wed, 12 Jun 2013 10:19:30 +0200 (CEST) Received: from gwhaus.rt.schenk (gwhaus.rt.schenk [172.22.0.4]) by mail.dmz.schenk (Postfix) with SMTP id 7E4EC1C04B4; Wed, 12 Jun 2013 10:19:30 +0200 (CEST) Received: from pcimr.localnet (pcimr.rt.schenk [172.22.10.20]) by gwhaus.rt.schenk (Postfix) with ESMTP id 5DAD5240854; Wed, 12 Jun 2013 10:19:30 +0200 (CEST) From: Rojhalat Ibrahim To: Scott Wood Subject: Re: [BUG] PCI related panic on powerpc based board with 3.10-rcX Date: Wed, 12 Jun 2013 10:19:30 +0200 Message-ID: <34279395.MbRViMjbAR@pcimr> User-Agent: KMail/4.10.3 (Linux/3.4.26; KDE/4.10.3; x86_64; ; ) In-Reply-To: <1370971739.18413.27@snotra> References: <1370971739.18413.27@snotra> MIME-Version: 1.0 Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Michael Guntsche X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tuesday 11 June 2013 12:28:59 Scott Wood wrote: > On 06/11/2013 12:09:42 PM, Michael Guntsche wrote: > > On Tue, Jun 11, 2013 at 7:00 PM, Scott Wood > > > > wrote: > > > On 06/11/2013 02:24:28 AM, Rojhalat Ibrahim wrote: > > >> On Monday 10 June 2013 17:52:33 Scott Wood wrote: > > >> > On 06/10/2013 12:07:43 PM, Michael Guntsche wrote: > > >> > > Good evening, > > >> > > > > >> > > This patch does not fix the problem, during boot the kernel > > > > still > > > > >> > > panics. I had a closer look at the commit and the following > > > > patch > > > > >> > > fixes it for me.... > > >> > > > > >> > > diff --git a/arch/powerpc/sysdev/fsl_pci.c > > >> > > b/arch/powerpc/sysdev/fsl_pci.c > > >> > > index 028ac1f..21b687f 100644 > > >> > > --- a/arch/powerpc/sysdev/fsl_pci.c > > >> > > +++ b/arch/powerpc/sysdev/fsl_pci.c > > >> > > @@ -814,7 +814,7 @@ int __init mpc83xx_add_bridge(struct > > > > device_node > > > > >> > > *dev) > > >> > > > > >> > > if (ret) > > >> > > > > >> > > goto err0; > > >> > > > > >> > > } else { > > >> > > > > >> > > - fsl_setup_indirect_pci(hose, rsrc_cfg.start, > > >> > > + setup_indirect_pci(hose, rsrc_cfg.start, > > >> > > > > >> > > rsrc_cfg.start + 4, 0); > > >> > > > > >> > > } > > >> > > > >> > The only difference here is that you're not setting hose->ops to > > >> > fsl_indirect_pci_ops. Do you know why that is helping, and what > > >> > hose->ops is set to instead? > > >> > > > >> > -Scott > > >> > > >> The difference is only the read function in hose->ops, which is > > > > set to > > > > >> indirect_read_config instead of fsl_indirect_read_config. > > >> > > >> fsl_indirect_read_config calls fsl_pcie_check_link, which is where > > > > the > > > > >> Oops > > >> occurs. > > > > > > Why is fsl_pcie_check_link being called for non-PCIe buses? > > > > > >> Mike, can you find out where exactly in fsl_pcie_check_link the > > > > bad access > > > > >> happens? Enabling CONFIG_DEBUG_BUGVERBOSE might help. > > > > > > Why does it matter? You shouldn't be calling that function at all. > > > > > > -Scott > > > > For the record BUGVERBOSE is already set with this build so this is > > the most detailed trace I get. And regarding Scott's remark, maybe I > > was not clear enough in my first report. This is a PCI only board so I > > also wondered about the call to fsl_pcie_check_link in the first > > place. > > Yes, I figured it was non-PCIe because the code change that you said > helped was on the non-PCIe branch of the if/else. Generally it's good > to explicitly mention the chip you're using, though. > > fsl_setup_indirect_pci should be renamed to fsl_setup_indirect_pcie. > Your patch above should be applied, and fsl_setup_indirect_pcie should > be moved into the booke/86xx ifdef to avoid an unused function warning. > > -Scott How about this patch? It uses setup_indirect_pci for the PCI case in mpc83xx_add_bridge. Additionally it adds a check in fsl_setup_indirect_pci to only use the modified read function in case of PCIe. Rojhalat diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 028ac1f..45670df 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -97,22 +97,23 @@ static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, return indirect_read_config(bus, devfn, offset, len, val); } -static struct pci_ops fsl_indirect_pci_ops = +static struct pci_ops fsl_indirect_pcie_ops = { .read = fsl_indirect_read_config, .write = indirect_write_config, }; +#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) + static void __init fsl_setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags) { setup_indirect_pci(hose, cfg_addr, cfg_data, flags); - hose->ops = &fsl_indirect_pci_ops; + if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) /* PCIe */ + hose->ops = &fsl_indirect_pcie_ops; } -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) - #define MAX_PHYS_ADDR_BITS 40 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; @@ -814,8 +815,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - fsl_setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. 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