Message ID | 20191120012859.23300-20-oohall@gmail.com (mailing list archive) |
---|---|
State | RFC |
Headers | show |
Series | [Very,RFC,01/46] powerpc/eeh: Don't attempt to restore VF config space after reset | expand |
Context | Check | Description |
---|---|---|
snowpatch_ozlabs/apply_patch | warning | Failed to apply on branch powerpc/merge (784eee1cc44801366d4f197e0ade7739ee8e1e83) |
snowpatch_ozlabs/apply_patch | warning | Failed to apply on branch powerpc/next (0695f8bca93ea0c57f0e8e21b4b4db70183b3d1c) |
snowpatch_ozlabs/apply_patch | warning | Failed to apply on branch linus/master (c74386d50fbaf4a54fd3fe560f1abc709c0cff4b) |
snowpatch_ozlabs/apply_patch | warning | Failed to apply on branch powerpc/fixes (7d6475051fb3d9339c5c760ed9883bc0a9048b21) |
snowpatch_ozlabs/apply_patch | warning | Failed to apply on branch linux-next (5d1131b4d61e52e5702e0fa4bcbec81ac7d6ef52) |
snowpatch_ozlabs/apply_patch | fail | Failed to apply to any branch |
On 20/11/2019 12:28, Oliver O'Halloran wrote: > We have a pci_dev so we can use the functions provided by the PCI core for > looking up capabilities. This should be safe since these are only called > when initialising the eeh_dev when the device is first probed and not in > the EEH recovery path where config accesses are blocked. > > This might cause a problem if an EEH event occured while probing the device, > but I'm pretty sure that's going to be broken anyway. > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> > --- > arch/powerpc/platforms/powernv/eeh-powernv.c | 67 ++------------------ I like this diffstat :) Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> > 1 file changed, 4 insertions(+), 63 deletions(-) > > diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c > index a974822c5097..b79aca8368c6 100644 > --- a/arch/powerpc/platforms/powernv/eeh-powernv.c > +++ b/arch/powerpc/platforms/powernv/eeh-powernv.c > @@ -358,65 +358,6 @@ static int pnv_eeh_write_config(struct eeh_dev *edev, > return pnv_pci_cfg_write(pdn, where, size, val); > } > > -static int pnv_eeh_find_cap(struct eeh_dev *edev, int cap) > -{ > - int pos = PCI_CAPABILITY_LIST; > - int cnt = 48; /* Maximal number of capabilities */ > - u32 status, id; > - > - /* Check if the device supports capabilities */ > - pnv_eeh_read_config(edev, PCI_STATUS, 2, &status); > - if (!(status & PCI_STATUS_CAP_LIST)) > - return 0; > - > - while (cnt--) { > - pnv_eeh_read_config(edev, pos, 1, &pos); > - if (pos < 0x40) > - break; > - > - pos &= ~3; > - pnv_eeh_read_config(edev, pos + PCI_CAP_LIST_ID, 1, &id); > - if (id == 0xff) > - break; > - > - /* Found */ > - if (id == cap) > - return pos; > - > - /* Next one */ > - pos += PCI_CAP_LIST_NEXT; > - } > - > - return 0; > -} > - > -static int pnv_eeh_find_ecap(struct eeh_dev *edev, int cap) > -{ > - u32 header; > - int pos = 256, ttl = (4096 - 256) / 8; > - > - if (!edev || !edev->pcie_cap) > - return 0; > - if (pnv_eeh_read_config(edev, pos, 4, &header) != PCIBIOS_SUCCESSFUL) > - return 0; > - else if (!header) > - return 0; > - > - while (ttl-- > 0) { > - if (PCI_EXT_CAP_ID(header) == cap && pos) > - return pos; > - > - pos = PCI_EXT_CAP_NEXT(header); > - if (pos < 256) > - break; > - > - if (pnv_eeh_read_config(edev, pos, 4, &header) != PCIBIOS_SUCCESSFUL) > - break; > - } > - > - return 0; > -} > - > /** > * pnv_eeh_probe - Do probe on PCI device > * @pdev: pci_dev to probe > @@ -458,10 +399,10 @@ static struct eeh_dev *pnv_eeh_probe_pdev(struct pci_dev *pdev) > > /* Initialize eeh device */ > edev->class_code = pdn->class_code; > - edev->pcix_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_PCIX); > - edev->pcie_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_EXP); > - edev->af_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_AF); > - edev->aer_cap = pnv_eeh_find_ecap(edev, PCI_EXT_CAP_ID_ERR); > + edev->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); > + edev->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); > + edev->af_cap = pci_find_capability(pdev, PCI_CAP_ID_AF); > + edev->aer_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); > if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { > edev->mode |= EEH_DEV_BRIDGE; > if (edev->pcie_cap) { >
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c index a974822c5097..b79aca8368c6 100644 --- a/arch/powerpc/platforms/powernv/eeh-powernv.c +++ b/arch/powerpc/platforms/powernv/eeh-powernv.c @@ -358,65 +358,6 @@ static int pnv_eeh_write_config(struct eeh_dev *edev, return pnv_pci_cfg_write(pdn, where, size, val); } -static int pnv_eeh_find_cap(struct eeh_dev *edev, int cap) -{ - int pos = PCI_CAPABILITY_LIST; - int cnt = 48; /* Maximal number of capabilities */ - u32 status, id; - - /* Check if the device supports capabilities */ - pnv_eeh_read_config(edev, PCI_STATUS, 2, &status); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - while (cnt--) { - pnv_eeh_read_config(edev, pos, 1, &pos); - if (pos < 0x40) - break; - - pos &= ~3; - pnv_eeh_read_config(edev, pos + PCI_CAP_LIST_ID, 1, &id); - if (id == 0xff) - break; - - /* Found */ - if (id == cap) - return pos; - - /* Next one */ - pos += PCI_CAP_LIST_NEXT; - } - - return 0; -} - -static int pnv_eeh_find_ecap(struct eeh_dev *edev, int cap) -{ - u32 header; - int pos = 256, ttl = (4096 - 256) / 8; - - if (!edev || !edev->pcie_cap) - return 0; - if (pnv_eeh_read_config(edev, pos, 4, &header) != PCIBIOS_SUCCESSFUL) - return 0; - else if (!header) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < 256) - break; - - if (pnv_eeh_read_config(edev, pos, 4, &header) != PCIBIOS_SUCCESSFUL) - break; - } - - return 0; -} - /** * pnv_eeh_probe - Do probe on PCI device * @pdev: pci_dev to probe @@ -458,10 +399,10 @@ static struct eeh_dev *pnv_eeh_probe_pdev(struct pci_dev *pdev) /* Initialize eeh device */ edev->class_code = pdn->class_code; - edev->pcix_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_PCIX); - edev->pcie_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_EXP); - edev->af_cap = pnv_eeh_find_cap(edev, PCI_CAP_ID_AF); - edev->aer_cap = pnv_eeh_find_ecap(edev, PCI_EXT_CAP_ID_ERR); + edev->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); + edev->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); + edev->af_cap = pci_find_capability(pdev, PCI_CAP_ID_AF); + edev->aer_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { edev->mode |= EEH_DEV_BRIDGE; if (edev->pcie_cap) {
We have a pci_dev so we can use the functions provided by the PCI core for looking up capabilities. This should be safe since these are only called when initialising the eeh_dev when the device is first probed and not in the EEH recovery path where config accesses are blocked. This might cause a problem if an EEH event occured while probing the device, but I'm pretty sure that's going to be broken anyway. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> --- arch/powerpc/platforms/powernv/eeh-powernv.c | 67 ++------------------ 1 file changed, 4 insertions(+), 63 deletions(-)