| Message ID | 20190903052407.16638-2-alastair@au1.ibm.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | powerpc: convert cache asm to C | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch next (c317052c95bef1f977b023158e5aa929215f443d) |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 16 lines checked |
Le 03/09/2019 à 07:23, Alastair D'Silva a écrit : > From: Alastair D'Silva <alastair@d-silva.org> > > When calling flush_icache_range with a size >4GB, we were masking > off the upper 32 bits, so we would incorrectly flush a range smaller > than intended. > > This patch replaces the 32 bit shifts with 64 bit ones, so that > the full size is accounted for. Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S ? Christophe > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > Cc: stable@vger.kernel.org > --- > arch/powerpc/kernel/misc_64.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S > index b55a7b4cb543..9bc0aa9aeb65 100644 > --- a/arch/powerpc/kernel/misc_64.S > +++ b/arch/powerpc/kernel/misc_64.S > @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 /* ensure we get enough */ > lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 1: dcbst 0,r6 > @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 > lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 2: icbi 0,r6 >
On Sat, 2019-09-14 at 09:46 +0200, Christophe Leroy wrote: > > Le 03/09/2019 à 07:23, Alastair D'Silva a écrit : > > From: Alastair D'Silva <alastair@d-silva.org> > > > > When calling flush_icache_range with a size >4GB, we were masking > > off the upper 32 bits, so we would incorrectly flush a range > > smaller > > than intended. > > > > This patch replaces the 32 bit shifts with 64 bit ones, so that > > the full size is accounted for. > > Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S > ? > > Christophe Yes, there is. I'll fix it, but I wonder whether anything calls it? I asked Google, and every mention of it was in the kernel source or mailing list. Maybe BenH can chime in?
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index b55a7b4cb543..9bc0aa9aeb65 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 1: dcbst 0,r6 @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 2: icbi 0,r6