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[193.116.72.140]) by smtp.gmail.com with ESMTPSA id h12sm8235847pje.12.2019.06.19.22.16.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 19 Jun 2019 22:16:37 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 45/52] powerpc/64s/exception: machine check windup restore cfar for host delivery Date: Thu, 20 Jun 2019 15:14:52 +1000 Message-Id: <20190620051459.29573-46-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190620051459.29573-1-npiggin@gmail.com> References: <20190620051459.29573-1-npiggin@gmail.com> MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Bare metal machine checks run an "early" handler in real mode which potentially flushes faulting translation structures, among other things, before running the main handler which reports the event. The main handler runs as a normal interrupt handler, after a "windup" that sets registers back as they were at interrupt entry. CFAR does not get restored by the windup code, so add that. The current handler does not appear to use CFAR anywhere, because the main handler is not run if the MCE happens in kernel-mode and the user-mode message is not a register trace. However it may be useful in some cases or future changes (xmon, panic on mce, etc). Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/exceptions-64s.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 61c96502d2a8..ab22af2509d8 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -1205,6 +1205,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) 9: /* Deliver the machine check to host kernel in V mode. */ +BEGIN_FTR_SECTION + ld r10,ORIG_GPR3(r1) + mtspr SPRN_CFAR,r10 +END_FTR_SECTION_IFSET(CPU_FTR_CFAR) MACHINE_CHECK_HANDLER_WINDUP EXCEPTION_PROLOG_0 PACA_EXMC EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0