From patchwork Thu Jun 29 07:12:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 782071 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyrZ209Llz9s75 for ; Thu, 29 Jun 2017 17:16:42 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="akfgMSan"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wyrZ163t7zDr4K for ; Thu, 29 Jun 2017 17:16:41 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="akfgMSan"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wyrV33zZJzDr3x for ; Thu, 29 Jun 2017 17:13:15 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="akfgMSan"; dkim-atps=neutral Received: by mail-pg0-x241.google.com with SMTP id u62so10887501pgb.0 for ; Thu, 29 Jun 2017 00:13:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zODbIweVpumcXOZmsJzeN+APh+16lMuF21OZfxm/Gq4=; b=akfgMSanluq9dU4TGLeH2kieJcrRouOcOM7Rto9dY/Gh8aQJUamEqW8bJlHtYXoXl6 N7ERsfG+KJZh24dnYBJ+uCQLHI1WsTNP4tcm97EmN6O9npK5iuHfYykWiSEkbQhYgYtR B69tZ5b/DAJzI/sHE3XpOmc1i4wbc8ae7Mf8Qp+Ur4kDFL2iMXuIjo2M+coZNxLa6lHZ C6jxSfglhLrQ8qz9sCynjKIuUi0N8ckyiZkCAJ8FsD3fMiKy0EI6AGhe+QRfH0o9NBRh 6QXXoOXd7W6LJDB28fci7IhvJZ37FqCuStEymbi2IWpySfuASTmCzef06ocoIA7p0sJU 6pew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zODbIweVpumcXOZmsJzeN+APh+16lMuF21OZfxm/Gq4=; b=UPbsEpxCAGZ6+cwRUD0UZKkUdovW57pVfp3pI9CDBQLCVnVr1XlCOgSqP2ue7E9Ewc pfz88d4H2uBB844JXM62Z8bfZ9tHhhBOF2VfaD0x25CMZ2wuYFRBWhzuaM5ZpRGIafc6 5JTvc6T9DWnauE6Ngj+Iz+d86IGTs4I5I5SChXfEIsOXiOBwhsPqAyzRgCppZuuJ+Zcl RdlRM8os5F0zDCUGa+i4jMyYMTSVbh5y7c1K4ugYgcAq7uGYTlW2fwekOvTfeHaqSRah wkiYc0zJ9LQfbMxjhbr9DQQYC4L726uJGDA1qn1CgvH4qGiNkKAL/WdADEfntBzcNKPj FX8g== X-Gm-Message-State: AKS2vOwkJixAIOfY59AgH2+zYSL5yZ0dMR3zrCtVpb53j5eAwEBhNoKA It72mUtHNFsUggi/ X-Received: by 10.99.97.146 with SMTP id v140mr14525328pgb.62.1498720393678; Thu, 29 Jun 2017 00:13:13 -0700 (PDT) Received: from flat-canetoad.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id a29sm9821658pfg.30.2017.06.29.00.13.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Jun 2017 00:13:13 -0700 (PDT) From: Oliver O'Halloran To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 1/4] powerpc/smp: Use cpu_to_chip_id() to find core siblings Date: Thu, 29 Jun 2017 17:12:53 +1000 Message-Id: <20170629071256.8159-2-oohall@gmail.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170629071256.8159-1-oohall@gmail.com> References: <20170629071256.8159-1-oohall@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, Oliver O'Halloran Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" When building the CPU scheduler topology the kernel uses the ibm,chipid property from the devicetree to group logical CPUs. Currently the DT search for this property is open-coded in smp.c and this functionality is a duplication of what's in cpu_to_chip_id() already. This patch removes the existing search in favor of that. It's worth mentioning that the semantics of the search are different in cpu_to_chip_id(). When there is no ibm,chipid in the CPUs node it will also search /cpus and / for the property, but this should not effect the output topology. Signed-off-by: Oliver O'Halloran --- arch/powerpc/kernel/smp.c | 37 +++++++++++-------------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index dbcd22e09a2c..40f1f268be83 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -829,19 +829,11 @@ EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); static void traverse_siblings_chip_id(int cpu, bool add, int chipid) { - const struct cpumask *mask; - struct device_node *np; - int i, plen; - const __be32 *prop; + const struct cpumask *mask = add ? cpu_online_mask : cpu_present_mask; + int i; - mask = add ? cpu_online_mask : cpu_present_mask; for_each_cpu(i, mask) { - np = of_get_cpu_node(i, NULL); - if (!np) - continue; - prop = of_get_property(np, "ibm,chip-id", &plen); - if (prop && plen == sizeof(int) && - of_read_number(prop, 1) == chipid) { + if (cpu_to_chip_id(i) == chipid) { if (add) { cpumask_set_cpu(cpu, cpu_core_mask(i)); cpumask_set_cpu(i, cpu_core_mask(cpu)); @@ -850,7 +842,6 @@ static void traverse_siblings_chip_id(int cpu, bool add, int chipid) cpumask_clear_cpu(i, cpu_core_mask(cpu)); } } - of_node_put(np); } } @@ -880,21 +871,15 @@ static void traverse_core_siblings(int cpu, bool add) { struct device_node *l2_cache, *np; const struct cpumask *mask; - int i, chip, plen; - const __be32 *prop; + int chip_id; + int i; - /* First see if we have ibm,chip-id properties in cpu nodes */ - np = of_get_cpu_node(cpu, NULL); - if (np) { - chip = -1; - prop = of_get_property(np, "ibm,chip-id", &plen); - if (prop && plen == sizeof(int)) - chip = of_read_number(prop, 1); - of_node_put(np); - if (chip >= 0) { - traverse_siblings_chip_id(cpu, add, chip); - return; - } + /* threads that share a chip-id are considered siblings */ + chip_id = cpu_to_chip_id(cpu); + + if (chip_id >= 0) { + traverse_siblings_chip_id(cpu, add, chip_id); + return; } l2_cache = cpu_to_l2cache(cpu);