diff mbox

powerpc/64s: catch external interrupts going to host in POWER9

Message ID 20170413001252.250018c4@roar.ozlabs.ibm.com
State New
Headers show

Commit Message

Nicholas Piggin April 12, 2017, 2:12 p.m. UTC
On Wed, 12 Apr 2017 23:45:42 +1000
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:

> On Wed, 2017-04-12 at 23:11 +1000, Nicholas Piggin wrote:
> > After setting LPES0 in the host on POWER9, the host external interrupt
> > handler no longer works correctly, because it's set to HV mode (HSRR)
> > for POWER7/8 with LPES0 clear. We don't expect to get any EE in the host
> > with XIVE, but it seems preferable to catch unexpected interrupts in case
> > there are bugs or unexpected behaviour.
> >   
> > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>  
> > ---  
> 
> No. Let's just get LPES back to P8 value in the host, we don't care as
> we don't get those EEs on normal systems. Then make sure KVM properly
> sets it the way we want when setting up the guest LPCR (which it should
> be doing with my patches).
> Much simpler patch...


Yeah sure that sounds good. How's this then?

---
 arch/powerpc/kernel/exceptions-64s.S | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

Comments

Benjamin Herrenschmidt April 12, 2017, 9:34 p.m. UTC | #1
On Thu, 2017-04-13 at 00:12 +1000, Nicholas Piggin wrote:
> Yeah sure that sounds good. How's this then?

I suppose so :-) When I was testing all that I had a "b ." at 0x500 and
0x4500 and I didn't hit them :)
Nicholas Piggin April 13, 2017, 1:52 a.m. UTC | #2
On Thu, 13 Apr 2017 07:34:51 +1000
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:

> On Thu, 2017-04-13 at 00:12 +1000, Nicholas Piggin wrote:
> > Yeah sure that sounds good. How's this then?  
> 
> I suppose so :-) When I was testing all that I had a "b ." at 0x500 and
> 0x4500 and I didn't hit them :)

If only for the benefit of poorly configured systemsim users
like me. Could remove it when the dust settles.
diff mbox

Patch

diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 857bf7c5b946..c78165e5fb77 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -735,8 +735,20 @@  EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
 
 TRAMP_KVM(PACA_EXGEN, 0x500)
 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
-EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
 
+EXC_COMMON_BEGIN(hardware_interrupt_common)
+BEGIN_FTR_SECTION
+	/*
+	 * The POWER9 XIVE interrupt controller should be configured to send
+	 * all interrupts to the host as HVI, even with the OPAL XICS
+	 * emulation, so HVMODE should never see a 0x500 interrupt. However we
+	 * catch it in case of a bug.
+	 */
+	b	unknown_host_ee_common
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
+	STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt_common, do_IRQ)
+
+EXC_COMMON_ASYNC(unknown_host_ee_common, 0x500, unknown_exception)
 
 EXC_REAL(alignment, 0x600, 0x100)
 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)