From patchwork Wed May 18 21:04:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 96235 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 00AA4100804 for ; Thu, 19 May 2011 07:06:30 +1000 (EST) Received: from VA3EHSOBE009.bigfish.com (va3ehsobe006.messaging.microsoft.com [216.32.180.16]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Cybertrust SureServer Standard Validation CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 7FAB6B6F5A for ; Thu, 19 May 2011 07:05:16 +1000 (EST) Received: from mail24-va3-R.bigfish.com (10.7.14.254) by VA3EHSOBE009.bigfish.com (10.7.40.29) with Microsoft SMTP Server id 14.1.225.22; Wed, 18 May 2011 21:05:06 +0000 Received: from mail24-va3 (localhost.localdomain [127.0.0.1]) by mail24-va3-R.bigfish.com (Postfix) with ESMTP id 63F961A18088; Wed, 18 May 2011 21:05:06 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail24-va3 (localhost.localdomain [127.0.0.1]) by mail24-va3 (MessageSwitch) id 1305752706157293_6647; Wed, 18 May 2011 21:05:06 +0000 (UTC) Received: from VA3EHSMHS007.bigfish.com (unknown [10.7.14.238]) by mail24-va3.bigfish.com (Postfix) with ESMTP id 17BC715D8050; Wed, 18 May 2011 21:05:06 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS007.bigfish.com (10.7.99.17) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 18 May 2011 21:04:55 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.270.2; Wed, 18 May 2011 16:04:54 -0500 Received: from schlenkerla.am.freescale.net (schlenkerla.am.freescale.net [10.82.121.12]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p4IL4rsT029994; Wed, 18 May 2011 16:04:54 -0500 (CDT) Date: Wed, 18 May 2011 16:04:53 -0500 From: Scott Wood To: Subject: [PATCH 1/7] powerpc/mm: 64-bit 4k: use page-sized PMDs Message-ID: <20110518210453.GA29500@schlenkerla.am.freescale.net> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com Cc: linuxppc-dev@lists.ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This allows a virtual page table to be used at the PMD rather than the PTE level. Rather than adjust the constant in pgd_index() (or ignore it, as too-large values don't hurt as long as overly large addresses aren't passed in), go back to using PTRS_PER_PGD. The overflow comment seems to apply to a very old implementation of free_pgtables that used pgd_index() (unfortunately the commit message, if you seek it out in the historic tree, doesn't mention any details about the overflow). The existing value was numerically indentical to the old 4K-page PTRS_PER_PGD, so using it shouldn't produce an overflow where it's not otherwise possible. Also get rid of the incorrect comment at the top of pgtable-ppc64-4k.h. Signed-off-by: Scott Wood --- arch/powerpc/include/asm/pgtable-ppc64-4k.h | 12 ++++-------- arch/powerpc/include/asm/pgtable-ppc64.h | 3 +-- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h index 6eefdcf..194005e 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h +++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h @@ -1,14 +1,10 @@ #ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H #define _ASM_POWERPC_PGTABLE_PPC64_4K_H -/* - * Entries per page directory level. The PTE level must use a 64b record - * for each page table entry. The PMD and PGD level use a 32b record for - * each entry by assuming that each entry is page aligned. - */ + #define PTE_INDEX_SIZE 9 -#define PMD_INDEX_SIZE 7 +#define PMD_INDEX_SIZE 9 #define PUD_INDEX_SIZE 7 -#define PGD_INDEX_SIZE 9 +#define PGD_INDEX_SIZE 7 #ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) @@ -19,7 +15,7 @@ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) -#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) +#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) /* PMD_SHIFT determines what a second-level page table entry can map */ diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index 2b09cd5..8bd1cd9 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -181,8 +181,7 @@ * Find an entry in a page-table-directory. We combine the address region * (the high order N bits) and the pgd portion of the address. */ -/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */ -#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff) +#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))