From patchwork Mon Mar 1 19:14:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Kleikamp X-Patchwork-Id: 46596 X-Patchwork-Delegate: jwboyer@gmail.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 7E3AE10271E for ; Tue, 2 Mar 2010 06:15:53 +1100 (EST) Received: by ozlabs.org (Postfix) id 080FD100B6C; Tue, 2 Mar 2010 06:14:28 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e33.co.us.ibm.com", Issuer "Equifax" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 9E327100B4C for ; Tue, 2 Mar 2010 06:14:27 +1100 (EST) Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by e33.co.us.ibm.com (8.14.3/8.13.1) with ESMTP id o21JAvGS005445 for ; Mon, 1 Mar 2010 12:10:57 -0700 Received: from d03av05.boulder.ibm.com (d03av05.boulder.ibm.com [9.17.195.85]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o21JEEnp118328 for ; Mon, 1 Mar 2010 12:14:15 -0700 Received: from d03av05.boulder.ibm.com (loopback [127.0.0.1]) by d03av05.boulder.ibm.com (8.14.3/8.13.1/NCO v10.0 AVout) with ESMTP id o21JEDXf024364 for ; Mon, 1 Mar 2010 12:14:13 -0700 Received: from norville.austin.ibm.com (sig-9-65-209-89.mts.ibm.com [9.65.209.89]) by d03av05.boulder.ibm.com (8.14.3/8.13.1/NCO v10.0 AVin) with ESMTP id o21JEC7N024342; Mon, 1 Mar 2010 12:14:12 -0700 Date: Mon, 1 Mar 2010 12:14:12 -0700 From: Dave Kleikamp To: linuxppc-dev list Message-Id: <20100301191411.20987.82569.sendpatchset@norville.austin.ibm.com> In-Reply-To: <20100301191255.20987.84668.sendpatchset@norville.austin.ibm.com> References: <20100301191255.20987.84668.sendpatchset@norville.austin.ibm.com> Subject: [RFC: PATCH 11/13] powerpc/476: Software workaround to fix dcr read/write sequencing. Cc: Torez Smith X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org powerpc/476: Software workaround to fix dcr read/write sequencing. From: Dave Kleikamp Copy the register containing the dcr address to a spr before mfdcrx or mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use as a dummy register, as it is only otherwise used by critical interrupts, and we don't care if what we write is overwritten. Ideally, would only do this when CPU_FTR_476_DD1_1 is set, but I'm not getting the feature macros working in inlined assembler. The dummy store is pretty cheap though, so I'm doing it unconditionally for 47x. Signed-off-by: Dave Kleikamp --- arch/powerpc/include/asm/dcr-native.h | 24 ++++++++++++++++++++++-- 1 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h index 7d2e623..768ce50 100644 --- a/arch/powerpc/include/asm/dcr-native.h +++ b/arch/powerpc/include/asm/dcr-native.h @@ -50,14 +50,34 @@ extern unsigned int __mfdcr(unsigned int reg); static inline unsigned int mfdcrx(unsigned int reg) { unsigned int ret; - asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)" + asm volatile( +#ifdef CONFIG_PPC_47x + /* + * Workaround: move reg to an spr prior to mfdcrx instruction + */ + /* __stringify(BEGIN_FTR_SECTION) */ + "mtspr "__stringify(SPRN_SPRG_WSCRATCH_CRIT)",%1;" + /* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */ +#endif + ".long 0x7c000206 | (%0 << 21) | (%1 << 16)" : "=r" (ret) : "r" (reg)); return ret; } static inline void mtdcrx(unsigned int reg, unsigned int val) { - asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)" + asm volatile( +#ifdef CONFIG_PPC_47x + /* + * Workaround: move reg to an spr prior to mtdcrx instruction. + * (Would love to get the FTR_SECTION macros working for + * inlined assembler -- shaggy) + */ + /* __stringify(BEGIN_FTR_SECTION) */ + "mtspr "__stringify(SPRN_SPRG_WSCRATCH_CRIT)",%1;" + /* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */ +#endif + ".long 0x7c000306 | (%0 << 21) | (%1 << 16)" : : "r" (val), "r" (reg)); }