From patchwork Thu Sep 24 00:45:52 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rex Feany X-Patchwork-Id: 34202 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 24E99B8165 for ; Thu, 24 Sep 2009 11:10:32 +1000 (EST) Received: by ozlabs.org (Postfix) id 7F06AB7B79; Thu, 24 Sep 2009 11:00:25 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from bos-spam.mrv.com (mx5.mrv.com [140.179.254.12]) by ozlabs.org (Postfix) with ESMTP id 06901B7B77 for ; Thu, 24 Sep 2009 11:00:25 +1000 (EST) X-ASG-Debug-ID: 1253753154-53ea00020001-myxymE Received: from bosmail.bos.mrv.com (bosmail.bos.mrv.com [140.179.176.26]) by bos-spam.mrv.com with ESMTP id jYK8kckLKpvjnnFs; Wed, 23 Sep 2009 20:45:54 -0400 (EDT) X-Barracuda-Envelope-From: RFeany@mrv.com Received: from chmailsrv.int.mrv.com ([192.168.11.19]) by bosmail.bos.mrv.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 23 Sep 2009 20:46:46 -0400 Received: from jane.chatsunix.int.mrv.com ([192.168.11.80]) by chmailsrv.int.mrv.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 23 Sep 2009 17:46:43 -0700 X-Barracuda-BBL-IP: 192.168.11.19 X-Barracuda-RBL-IP: 192.168.11.19 Received: from compile2.chatsunix.int.mrv.com ([192.168.17.15]) by jane.chatsunix.int.mrv.com with esmtp (Exim 4.69) (envelope-from ) id 1MqcT2-0000GT-8r; Wed, 23 Sep 2009 17:45:52 -0700 Received: from rfeany by compile2.chatsunix.int.mrv.com with local (Exim 4.69) (envelope-from ) id 1MqcT2-0003D8-8C; Wed, 23 Sep 2009 17:45:52 -0700 Date: Wed, 23 Sep 2009 17:45:52 -0700 From: Rex Feany To: Benjamin Herrenschmidt X-ASG-Orig-Subj: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite Subject: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite Message-ID: <20090924004552.GA11737@compile2.chatsunix.int.mrv.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 24 Sep 2009 00:46:43.0882 (UTC) FILETIME=[7CC730A0:01CA3CB0] X-Barracuda-Connect: bosmail.bos.mrv.com[140.179.176.26] X-Barracuda-Start-Time: 1253753154 X-Barracuda-URL: http://140.179.128.126:8000/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at mrv.com X-Mailman-Approved-At: Thu, 24 Sep 2009 11:10:14 +1000 Cc: linuxppc-dev@ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org After upgrading to the latest kernel on my mpc875 userspace started running incredibly slow (hours to get to a shell, even!). I tracked it down to commit 8d30c14cab30d405a05f2aaceda1e9ad57800f36, that patch removed a work-around for the 8xx. Adding it back makes my problem go away. Signed-off-by: Rex Feany diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c index 627767d..d8e6725 100644 --- a/arch/powerpc/mm/pgtable.c +++ b/arch/powerpc/mm/pgtable.c @@ -30,6 +30,8 @@ #include #include +#include "mmu_decl.h" + static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur); static unsigned long pte_freelist_forced_free; @@ -119,7 +121,7 @@ void pte_free_finish(void) /* * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags() */ -static pte_t do_dcache_icache_coherency(pte_t pte) +static pte_t do_dcache_icache_coherency(pte_t pte, unsigned long addr) { unsigned long pfn = pte_pfn(pte); struct page *page; @@ -128,6 +130,17 @@ static pte_t do_dcache_icache_coherency(pte_t pte) return pte; page = pfn_to_page(pfn); +#ifdef CONFIG_8xx + /* On 8xx, cache control instructions (particularly + * "dcbst" from flush_dcache_icache) fault as write + * operation if there is an unpopulated TLB entry + * for the address in question. To workaround that, + * we invalidate the TLB here, thus avoiding dcbst + * misbehaviour. + */ + _tlbil_va(addr, 0 /* 8xx doesn't care about PID */); +#endif + if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) { pr_devel("do_dcache_icache_coherency... flushing\n"); flush_dcache_icache_page(page); @@ -198,7 +211,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte */ pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); if (pte_need_exec_flush(pte, 1)) - pte = do_dcache_icache_coherency(pte); + pte = do_dcache_icache_coherency(pte, addr); /* Perform the setting of the PTE */ __set_pte_at(mm, addr, ptep, pte, 0); @@ -216,7 +229,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, { int changed; if (!dirty && pte_need_exec_flush(entry, 0)) - entry = do_dcache_icache_coherency(entry); + entry = do_dcache_icache_coherency(entry, address); changed = !pte_same(*(ptep), entry); if (changed) { if (!(vma->vm_flags & VM_HUGETLB))