From patchwork Mon Jul 6 12:18:45 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Blanchard X-Patchwork-Id: 29496 X-Patchwork-Delegate: paulus@samba.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 779DAB6F20 for ; Mon, 6 Jul 2009 22:19:58 +1000 (EST) Received: by ozlabs.org (Postfix) id 69555DDD0C; Mon, 6 Jul 2009 22:19:58 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 67538DDD0B for ; Mon, 6 Jul 2009 22:19:58 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 31415B730F for ; Mon, 6 Jul 2009 22:19:19 +1000 (EST) Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 45110B6F20 for ; Mon, 6 Jul 2009 22:19:12 +1000 (EST) Received: by ozlabs.org (Postfix) id 280D9DDD01; Mon, 6 Jul 2009 22:19:12 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: by ozlabs.org (Postfix, from userid 1010) id 21537DDD0B; Mon, 6 Jul 2009 22:19:12 +1000 (EST) Date: Mon, 6 Jul 2009 22:18:45 +1000 From: Anton Blanchard To: mingo@elte.hu, a.p.zijlstra@chello.nl, paulus@samba.org, benh@kernel.crashing.org Subject: [PATCH] powerpc/perf_counter: Add alignment-faults and emulation-faults sw events Message-ID: <20090706121845.GD4391@kryten> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Hook up the alignment-faults and emulation-faults events for powerpc. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt --- Lots of duplication between PPC_WARN_EMULATED() and perf_swcounter_event() here. Maybe we need to create PPC_WARN_ALIGNMENT(), use it and hide all calls to perf_swcounter_event in the macros. Index: linux.trees.git/arch/powerpc/kernel/align.c =================================================================== --- linux.trees.git.orig/arch/powerpc/kernel/align.c 2009-07-06 21:50:53.000000000 +1000 +++ linux.trees.git/arch/powerpc/kernel/align.c 2009-07-06 22:10:41.000000000 +1000 @@ -25,6 +25,7 @@ #include #include #include +#include struct aligninfo { unsigned char len; @@ -707,6 +708,9 @@ */ CHECK_FULL_REGS(regs); + perf_swcounter_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, + regs->nip); + dsisr = regs->dsisr; /* Some processors don't provide us with a DSISR we can use here, Index: linux.trees.git/arch/powerpc/kernel/traps.c =================================================================== --- linux.trees.git.orig/arch/powerpc/kernel/traps.c 2009-07-06 21:50:53.000000000 +1000 +++ linux.trees.git/arch/powerpc/kernel/traps.c 2009-07-06 22:11:52.000000000 +1000 @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -759,6 +760,8 @@ /* Emulate the mfspr rD, PVR. */ if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(mfpvr); rd = (instword >> 21) & 0x1f; regs->gpr[rd] = mfspr(SPRN_PVR); @@ -767,6 +770,8 @@ /* Emulating the dcba insn is just a no-op. */ if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(dcba); return 0; } @@ -776,6 +781,8 @@ int shift = (instword >> 21) & 0x1c; unsigned long msk = 0xf0000000UL >> shift; + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(mcrxr); regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); regs->xer &= ~0xf0000000UL; @@ -784,18 +791,24 @@ /* Emulate load/store string insn. */ if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(string); return emulate_string_inst(regs, instword); } /* Emulate the popcntb (Population Count Bytes) instruction. */ if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(popcntb); return emulate_popcntb_inst(regs, instword); } /* Emulate isel (Integer Select) instruction */ if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(isel); return emulate_isel(regs, instword); } @@ -994,8 +1007,11 @@ #ifdef CONFIG_MATH_EMULATION errcode = do_mathemu(regs); - if (errcode >= 0) + if (errcode >= 0) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(math); + } switch (errcode) { case 0: @@ -1017,8 +1033,11 @@ #elif defined(CONFIG_8XX_MINIMAL_FPEMU) errcode = Soft_emulate_8xx(regs); - if (errcode >= 0) + if (errcode >= 0) { + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, + regs, regs->nip); PPC_WARN_EMULATED(8xx); + } switch (errcode) { case 0: @@ -1129,6 +1148,8 @@ flush_altivec_to_thread(current); + perf_swcounter_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, + regs->nip); PPC_WARN_EMULATED(altivec); err = emulate_altivec(regs); if (err == 0) {