From patchwork Mon Mar 16 14:21:04 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 24500 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id BF1A4DDFAD for ; Tue, 17 Mar 2009 01:21:27 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from protonic.prtnl (protonic.xs4all.nl [213.84.116.84]) by ozlabs.org (Postfix) with ESMTP id C0D6BDDF31 for ; Tue, 17 Mar 2009 01:21:07 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by protonic.prtnl (Postfix) with ESMTP id A467D29EC9; Mon, 16 Mar 2009 15:19:47 +0100 (CET) Received: from protonic.prtnl ([127.0.0.1]) by localhost (protonic [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 18531-09; Mon, 16 Mar 2009 15:19:47 +0100 (CET) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.prtnl (Postfix) with ESMTP id 6287329EBA; Mon, 16 Mar 2009 15:19:47 +0100 (CET) From: David Jander Organization: Protonic Holland To: Kumar Gala Subject: [RFC][PATCH v4] MPC5121 TLB errata workaround Date: Mon, 16 Mar 2009 15:21:04 +0100 User-Agent: KMail/1.9.10 MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200903161521.04979.david.jander@protonic.nl> X-Virus-Scanned: by amavisd-new at prtnl Cc: linuxppc-dev , Paul Mackerras , Wolfgang Denk , Gunnar Von Boehn X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Complete workaround for DTLB errata in MPC5121e processors of die M36P and older (all currently existing versions). Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table encoded in 32 bits of SPRG6 for chosing the TLB-way. Signed-off-by: David Jander --- mfspr r2,SPRN_SPRG3 @@ -612,9 +616,32 @@ DataStoreTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ + mfspr r3,SPRN_DMISS +#ifdef CONFIG_PPC_MPC512x +/* MPC512x: workaround for errata in die M36P and earlier: + * Implement LRW for TLB way. + */ + rlwinm r0,r3,17,27,31 /* Get Address bits 19:15 */ + li r1,1 + slw r0,r1,r0 /* Make bitmask */ + mfspr r2,SPRN_SPRG6 /* Get lrw table */ + and. r1,r2,r0 /* Check entry in lrw */ + beq- 0,113f /* 0? Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + andc r2,r2,r0 + mtspr SPRN_SPRG6,r2 + b 114f +113: + or r2,r2,r0 + mtspr SPRN_SPRG6,r2 +114: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS lis r1,PAGE_OFFSET@h /* check if kernel address */ cmplw 0,r1,r3 mfspr r2,SPRN_SPRG3 @@ -688,6 +715,29 @@ DataStoreTLBMiss: .globl mol_trampoline .set mol_trampoline, i0x2f00 +#ifdef CONFIG_PPC_MPC512x +e300_read_tlb_fix: + rlwinm r0,r3,17,27,31 /* Get Address bits 19:15 */ + li r1,1 + slw r0,r1,r0 /* Make bitmask */ + mfspr r2,SPRN_SPRG6 /* Get lrw table */ + and. r1,r2,r0 /* Check entry in lrw */ + beq- 0,113f /* 0? Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + andc r2,r2,r0 + mtspr SPRN_SPRG6,r2 + b 114f +113: + or r2,r2,r0 + mtspr SPRN_SPRG6,r2 +114: + b e300_read_tlb_fix_ret +#endif + . = 0x3000 AltiVecUnavailable: diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0f4fac5..6cc0cd3 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -540,9 +540,13 @@ DataLoadTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ + mfspr r3,SPRN_DMISS +#ifdef CONFIG_PPC_MPC512x + b e300_read_tlb_fix /* Code for TLB-errata workaround doesn't fit here */ +e300_read_tlb_fix_ret: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS lis r1,PAGE_OFFSET@h /* check if kernel address */ cmplw 0,r1,r3