From patchwork Fri Mar 13 10:20:59 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 24380 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 1CE98DE43E for ; Fri, 13 Mar 2009 21:18:35 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from protonic.prtnl (protonic.xs4all.nl [213.84.116.84]) by ozlabs.org (Postfix) with ESMTP id E3C54DE0AB for ; Fri, 13 Mar 2009 21:18:07 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by protonic.prtnl (Postfix) with ESMTP id 9855B29EC9; Fri, 13 Mar 2009 11:16:46 +0100 (CET) Received: from protonic.prtnl ([127.0.0.1]) by localhost (protonic [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 02624-08; Fri, 13 Mar 2009 11:16:46 +0100 (CET) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.prtnl (Postfix) with ESMTP id 4DE6029EBA; Fri, 13 Mar 2009 11:16:46 +0100 (CET) From: David Jander Organization: Protonic Holland To: "linuxppc-dev" Subject: [RFC] [PATCH v2] MPC5121 TLB errata workaround Date: Fri, 13 Mar 2009 11:20:59 +0100 User-Agent: KMail/1.9.10 MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200903131121.00077.david.jander@protonic.nl> X-Virus-Scanned: by amavisd-new at prtnl Cc: Paul Mackerras , Wolfgang Denk , Gunnar Von Boehn X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Complete workaround for DTLB errata in MPC5121e processors of die M36P and older (all currently existing versions). Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Signed-off-by: David Jander --- arch/powerpc/kernel/head_32.S | 65 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 65 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0f4fac5..a88b3aa 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -540,6 +540,10 @@ DataLoadTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ +#ifdef CONFIG_PPC_MPC512x + b TlbWo /* Code for TLB-errata workaround doesn't fit here */ +RFTlbWo: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS @@ -612,6 +616,31 @@ DataStoreTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ +#ifdef CONFIG_PPC_MPC512x +/* MPC512x: workaround for errata in die M36P and earlier: + * Implement LRW for TLB way. + */ + mfspr r3,SPRN_DMISS + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ + lis r2,lrw@ha /* Search index in lrw[] */ + addi r2,r2,lrw@l + tophys(r2,r2) + lwzx r1,r3,r2 /* Get item from lrw[] */ + cmpwi 0,r1,0 /* Was it way 0 last time? */ + beq- 0,113f /* Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + li r0,0 + stwx r0,r3,r2 /* Make lrw[] entry 0 */ + b 114f +113: + li r0,1 + stwx r0,r3,r2 /* Make lrw[] entry 1 */ +114: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS @@ -688,6 +717,34 @@ DataStoreTLBMiss: .globl mol_trampoline .set mol_trampoline, i0x2f00 +#ifdef CONFIG_PPC_MPC512x +TlbWo: +/* MPC512x: workaround for errata in die M36P and earlier: + * Implement LRW for TLB way. + */ + mfspr r3,SPRN_DMISS + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ + lis r2,lrw@ha /* Search index in lrw[] */ + addi r2,r2,lrw@l + tophys(r2,r2) + lwzx r1,r3,r2 /* Get item from lrw[] */ + cmpwi 0,r1,0 /* Was it way 0 last time? */ + beq- 0,113f /* Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + li r0,0 + stwx r0,r3,r2 /* Make lrw[] entry 0 */ + b 114f +113: + li r0,1 + stwx r0,r3,r2 /* Make lrw[] entry 1 */ +114: + b RFTlbWo +#endif + . = 0x3000 AltiVecUnavailable: @@ -1321,6 +1378,14 @@ intercept_table: .long 0, 0, 0, 0, 0, 0, 0, 0 .long 0, 0, 0, 0, 0, 0, 0, 0 .long 0, 0, 0, 0, 0, 0, 0, 0 + +#ifdef CONFIG_PPC_MPC512x +lrw: + .long 0, 0, 0, 0, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 +#endif /* Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table.