From patchwork Thu Mar 12 13:30:48 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 24342 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 69D4EDE1AD for ; Fri, 13 Mar 2009 00:29:39 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from protonic.prtnl (protonic.xs4all.nl [213.84.116.84]) by ozlabs.org (Postfix) with ESMTP id CBBF3DDF6F for ; Fri, 13 Mar 2009 00:28:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by protonic.prtnl (Postfix) with ESMTP id 2D4AD29EC9; Thu, 12 Mar 2009 14:26:41 +0100 (CET) Received: from protonic.prtnl ([127.0.0.1]) by localhost (protonic [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 05691-10; Thu, 12 Mar 2009 14:26:41 +0100 (CET) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.prtnl (Postfix) with ESMTP id EE3A529EBA; Thu, 12 Mar 2009 14:26:40 +0100 (CET) From: David Jander Organization: Protonic Holland To: "linuxppc-dev@ozlabs.org" Subject: Proposal: [PATCH] Workaround for MPC5121 DTLB errata Date: Thu, 12 Mar 2009 14:30:48 +0100 User-Agent: KMail/1.9.10 MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200903121430.49077.david.jander@protonic.nl> X-Virus-Scanned: by amavisd-new at prtnl X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Partial workaround for DTLB errata in MPC5121e processors of die M36P and older (all currently existing versions). Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix forces writes to go to way 0, which would speed up memory-copy operations where bits 15...19 of source and destination address are the same. Signed-off-by: David Jander --- arch/powerpc/kernel/head_32.S | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -614,6 +614,14 @@ DataStoreTLBMiss: */ mfctr r0 /* Get PTE (linux-style) and check access */ +#ifdef CONFIG_PPC_MPC512x +/* MPC512x: (partial) workaround for errata in die M36P and earlier: + * Force writes to Way 0 (reads are always way 1) + */ + mfspr r3,SPRN_SRR1 + rlwinm r3,r3,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r3 +#endif mfspr r3,SPRN_DMISS lis r1,PAGE_OFFSET@h /* check if kernel address */ cmplw 0,r1,r3