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Thu, 21 Jan 2021 16:48:50 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 10LGmlT338339004 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Jan 2021 16:48:47 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A8CC211C04C; Thu, 21 Jan 2021 16:48:47 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7E96A11C04A; Thu, 21 Jan 2021 16:48:46 +0000 (GMT) Received: from thinktux.local (unknown [9.199.63.224]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 21 Jan 2021 16:48:46 +0000 (GMT) Subject: [PATCH] lib/sstep: Fix incorrect return from analyze_instr() From: Ananth N Mavinakayanahalli To: linuxppc-dev@lists.ozlabs.org Date: Thu, 21 Jan 2021 22:18:45 +0530 Message-ID: <161124771457.333703.14641179082577500423.stgit@thinktux.local> User-Agent: StGit/0.23 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-21_08:2021-01-21, 2021-01-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 malwarescore=0 mlxlogscore=980 priorityscore=1501 clxscore=1011 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101210088 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: naveen.n.rao@linux.ibm.com, paulus@samba.org, sandipan@linux.ibm.com, ravi.bangoria@linux.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" We currently just percolate the return value from analyze_instr() to the caller of emulate_step(), especially if it is a -1. For one particular case (opcode = 4) for instructions that aren't currently emulated, we are returning 'should not be single-stepped' while we should have returned 0 which says 'did not emulate, may have to single-step'. Signed-off-by: Ananth N Mavinakayanahalli Tested-by: Naveen N. Rao Reviewed-by: Naveen N. Rao < naveen.n.rao@linux.vnet.ibm.com> Reviewed-by: Sandipan Das Acked-by: Ananth N Mavinakayanahalli --- arch/powerpc/lib/sstep.c | 49 +++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 5a425a4a1d88..a3a0373843cd 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1445,34 +1445,39 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, #ifdef __powerpc64__ case 4: - if (!cpu_has_feature(CPU_FTR_ARCH_300)) - return -1; - - switch (word & 0x3f) { - case 48: /* maddhd */ - asm volatile(PPC_MADDHD(%0, %1, %2, %3) : - "=r" (op->val) : "r" (regs->gpr[ra]), - "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); - goto compute_done; + /* + * There are very many instructions with this primary opcode + * introduced in the ISA as early as v2.03. However, the ones + * we currently emulate were all introduced with ISA 3.0 + */ + if (cpu_has_feature(CPU_FTR_ARCH_300)) { + switch (word & 0x3f) { + case 48: /* maddhd */ + asm volatile(PPC_MADDHD(%0, %1, %2, %3) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); + goto compute_done; - case 49: /* maddhdu */ - asm volatile(PPC_MADDHDU(%0, %1, %2, %3) : - "=r" (op->val) : "r" (regs->gpr[ra]), - "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); - goto compute_done; + case 49: /* maddhdu */ + asm volatile(PPC_MADDHDU(%0, %1, %2, %3) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); + goto compute_done; - case 51: /* maddld */ - asm volatile(PPC_MADDLD(%0, %1, %2, %3) : - "=r" (op->val) : "r" (regs->gpr[ra]), - "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); - goto compute_done; + case 51: /* maddld */ + asm volatile(PPC_MADDLD(%0, %1, %2, %3) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); + goto compute_done; + } } /* - * There are other instructions from ISA 3.0 with the same - * primary opcode which do not have emulation support yet. + * Rest of the instructions with this primary opcode do not + * have emulation support yet. */ - return -1; + op->type = UNKNOWN; + return 0; #endif case 7: /* mulli */