From patchwork Wed Sep 12 19:40:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Breno Leitao X-Patchwork-Id: 969175 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 429XKY0nmyz9sCW for ; Thu, 13 Sep 2018 05:44:17 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=debian.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 429XKX5qJSzF39K for ; Thu, 13 Sep 2018 05:44:16 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=debian.org X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=debian.org (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=leitao@debian.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=debian.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 429XFF58WSzF3D1 for ; Thu, 13 Sep 2018 05:40:33 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8CJYa5C052558 for ; Wed, 12 Sep 2018 15:40:30 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mf60384hw-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 12 Sep 2018 15:40:30 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 12 Sep 2018 13:40:27 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8CJeQrp42205350 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Sep 2018 12:40:26 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C99727805E; Wed, 12 Sep 2018 13:40:26 -0600 (MDT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B43A78063; Wed, 12 Sep 2018 13:40:24 -0600 (MDT) Received: from debra.ibm.com (unknown [9.85.149.11]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 12 Sep 2018 13:40:24 -0600 (MDT) From: Breno Leitao To: linuxppc-dev@lists.ozlabs.org Subject: [RFC PATCH 01/11] powerpc/tm: Reclaim transaction on kernel entry Date: Wed, 12 Sep 2018 16:40:09 -0300 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org> References: <1536781219-13938-1-git-send-email-leitao@debian.org> X-TM-AS-GCONF: 00 x-cbid: 18091219-0016-0000-0000-0000092C7872 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009709; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01087369; UDB=6.00561487; IPR=6.00867382; MB=3.00023256; MTD=3.00000008; XFM=3.00000015; UTC=2018-09-12 19:40:29 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091219-0017-0000-0000-00004054677B Message-Id: <1536781219-13938-2-git-send-email-leitao@debian.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-12_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=976 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809120195 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, gromero@linux.vnet.ibm.com, Breno Leitao , ldufour@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This patch creates a macro that will be invoked on all entrance to the kernel, so, in kernel space the transaction will be completely reclaimed and not suspended anymore. This patchset checks if we are coming from PR, if not, skip. This is useful when there is a irq_replay() being called after recheckpoint, when the IRQ is re-enable. In this case, we do not want to re-reclaim and re-recheckpoint, thus, if not coming from PR, skip it completely. This macro does not care about TM SPR also, it will only be saved and restore in the context switch code now on. This macro will return 0 or 1 in r3 register, to specify if a reclaim was executed or not. This patchset is based on initial work done by Cyril: https://patchwork.ozlabs.org/cover/875341/ Signed-off-by: Breno Leitao --- arch/powerpc/include/asm/exception-64s.h | 46 ++++++++++++++++++++++++ arch/powerpc/kernel/entry_64.S | 10 ++++++ arch/powerpc/kernel/exceptions-64s.S | 12 +++++-- 3 files changed, 66 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index a86feddddad0..db90b6d7826e 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -36,6 +36,7 @@ */ #include #include +#include /* PACA save area offsets (exgen, exmc, etc) */ #define EX_R9 0 @@ -686,10 +687,54 @@ BEGIN_FTR_SECTION \ beql ppc64_runlatch_on_trampoline; \ END_FTR_SECTION_IFSET(CPU_FTR_CTRL) +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + +/* + * This macro will reclaim a transaction if called when coming from userspace + * (MSR.PR = 1) and if the transaction state is active or suspended. + * + * Since we don't want to reclaim when coming from kernel, for instance after + * a trechkpt. or a IRQ replay, the live MSR is not useful and instead of it the + * MSR from thread stack is used to check the MSR.PR bit. + * This macro has one argument which is the cause that will be used by treclaim. + * and returns in r3 '1' if the reclaim happens or '0' if reclaim didn't + * happen, which is useful to know what registers were clobbered. + * + * NOTE: If addition registers are clobbered here, make sure the callee + * function restores them before proceeding. + */ +#define TM_KERNEL_ENTRY(cause) \ + ld r3, _MSR(r1); \ + andi. r0, r3, MSR_PR; /* Coming from userspace? */ \ + beq 1f; /* Skip reclaim if MSR.PR != 1 */ \ + rldicl. r0, r3, (64-MSR_TM_LG), 63; /* Is TM enabled? */ \ + beq 1f; /* Skip reclaim if TM is off */ \ + rldicl. r0, r3, (64-MSR_TS_LG), 62; /* Is active */ \ + beq 1f; /* Skip reclaim if neither */ \ + /* \ + * If there is a transaction active or suspended, save the \ + * non-volatile GPRs if they are not already saved. \ + */ \ + bl save_nvgprs; \ + /* \ + * Soft disable the IRQs, otherwise it might cause a CPU hang. \ + */ \ + RECONCILE_IRQ_STATE(r10, r11); \ + li r3, cause; \ + bl tm_reclaim_current; \ + li r3, 1; /* Reclaim happened */ \ + b 2f; \ +1: li r3, 0; /* Reclaim didn't happen */ \ +2: +#else +#define TM_KERNEL_ENTRY(cause) +#endif + #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ EXCEPTION_PROLOG_COMMON(trap, area); \ /* Volatile regs are potentially clobbered here */ \ additions; \ + TM_KERNEL_ENTRY(TM_CAUSE_MISC); \ addi r3,r1,STACK_FRAME_OVERHEAD; \ bl hdlr; \ b ret @@ -704,6 +749,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CTRL) EXCEPTION_PROLOG_COMMON_3(trap); \ /* Volatile regs are potentially clobbered here */ \ additions; \ + TM_KERNEL_ENTRY(TM_CAUSE_MISC); \ addi r3,r1,STACK_FRAME_OVERHEAD; \ bl hdlr diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 2206912ea4f0..c38677b7442c 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -131,6 +131,16 @@ BEGIN_FW_FTR_SECTION END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */ +#if CONFIG_PPC_TRANSACTIONAL_MEM + TM_KERNEL_ENTRY(TM_CAUSE_SYSCALL) + cmpdi r3, 0x1 + bne 44f + /* Restore from r4 to r12 */ + REST_8GPRS(4,r1) +44: /* treclaim was not called, just restore r3 and r0 */ + REST_GPR(3, r1) + REST_GPR(0, r1) +#endif /* * A syscall should always be called with interrupts enabled * so we just unconditionally hard-enable here. When some kind diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index ea04dfb8c092..78aba71a4b2d 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -805,6 +805,7 @@ EXC_COMMON_BEGIN(alignment_common) std r3,_DAR(r1) std r4,_DSISR(r1) bl save_nvgprs + TM_KERNEL_ENTRY(TM_CAUSE_ALIGNMENT) RECONCILE_IRQ_STATE(r10, r11) addi r3,r1,STACK_FRAME_OVERHEAD bl alignment_exception @@ -839,6 +840,8 @@ EXC_COMMON_BEGIN(program_check_common) b 3f /* Jump into the macro !! */ 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) bl save_nvgprs + ld r3, _MSR(r1) + TM_KERNEL_ENTRY(TM_CAUSE_FAC_UNAV) RECONCILE_IRQ_STATE(r10, r11) addi r3,r1,STACK_FRAME_OVERHEAD bl program_check_exception @@ -1738,7 +1741,9 @@ do_hash_page: /* Here we have a page fault that hash_page can't handle. */ handle_page_fault: -11: andis. r0,r4,DSISR_DABRMATCH@h +11: TM_KERNEL_ENTRY(TM_CAUSE_TLBI) + ld r4,_DSISR(r1) + andis. r0,r4,DSISR_DABRMATCH@h bne- handle_dabr_fault ld r4,_DAR(r1) ld r5,_DSISR(r1) @@ -1769,6 +1774,8 @@ handle_dabr_fault: */ 13: bl save_nvgprs mr r5,r3 + TM_KERNEL_ENTRY(TM_CAUSE_TLBI) + REST_GPR(3,r1) addi r3,r1,STACK_FRAME_OVERHEAD ld r4,_DAR(r1) bl low_hash_fault @@ -1783,7 +1790,8 @@ handle_dabr_fault: * the access, or panic if there isn't a handler. */ 77: bl save_nvgprs - mr r4,r3 + TM_KERNEL_ENTRY(TM_CAUSE_TLBI) + ld r4,_DAR(r1) addi r3,r1,STACK_FRAME_OVERHEAD li r5,SIGSEGV bl bad_page_fault