From patchwork Thu Jan 11 10:11:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 859034 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zHN9b4PPXz9s7M for ; Thu, 11 Jan 2018 21:56:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ivuKtYDn"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zHN9b39mNzF0Rd for ; Thu, 11 Jan 2018 21:56:51 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ivuKtYDn"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=wei.guo.simon@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ivuKtYDn"; dkim-atps=neutral Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zHMBs44tHzF0Xq for ; Thu, 11 Jan 2018 21:12:53 +1100 (AEDT) Received: by mail-pg0-x241.google.com with SMTP id f14so1845451pga.10 for ; Thu, 11 Jan 2018 02:12:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=76nfUDlInTFl3nLdx4sHeN/LfTfQKNVKJfLb1/F9no8=; b=ivuKtYDnMZpVKBReuSPIEKhtuoRLbpx3g0aHVHJUjveJFFEBQ/1gUWpfPtVKRTC8KP 9tEcJ6Kaqv6uhi+4qbu+wxTORLKvWo60BLcqUiZgPegcaMZDIszE3cixqDp8naAn1Z9A sUMc+rQYs5ZFFaMGprobEZvjbvfPQERz90lNPSwaoOYkbuvaO6kOEqn+xBcUS+YkwTgG XGCJcB32y0gvLD7e42cTr/n2Vg81adOk99oOdOpb1W3E+F9RB1YVNkKCwBIZC8uBUZ9M 0QNZfe+FOZqdjTi733+zwcmxY7r1nt/Cny6Yqd+E4n8Kw0NI/QGsUJ5mUF04xo1H3b6K 2B5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=76nfUDlInTFl3nLdx4sHeN/LfTfQKNVKJfLb1/F9no8=; b=HE4FhY4Dzcm153MGuThkgliT7tgaOvHlJmErDQ0C7U3K1A8vOIzUOe7IiOJO6cMv+H 4fGHyj8oELWAEvBNby7kUU+YADsvuttpHxhgkfk74dyAzbxVm9IBiL6pMI7Vw8tW7fDz SeJYOoLWVYSntoCszaDJhCR7PEuilZo4VbT7RlCXxS5RjAcmCu90GvjwlxlfxBZmcT/o ZEMk0RSR7mFCAcfRrnah27H4EMcag76WbHyvAp+QJXwntEHw/r83J/6br35pbnTHJMOq Sb+mol2/UqXq/jVVd2XxY4Hqd9deYIjhonh1jOXpDunH5/onR6/ZmCQd10Hbi14jHTz0 D0IQ== X-Gm-Message-State: AKGB3mLZoZwmmKELxMhjF0LeqEpdShBIq+b97sTs+l2WCpfRDtkKYrcN N2kjzf9ygFtHLGD2FtcRgdwVWg== X-Google-Smtp-Source: ACJfBotgp49uv0tOtpkNLgAyz6iSwZd6hPCa7mNpmUR+twvYFm9eiDJpAJBI2tNAJx0vtgy7zBwWwg== X-Received: by 10.84.131.162 with SMTP id d31mr21805268pld.193.1515665571527; Thu, 11 Jan 2018 02:12:51 -0800 (PST) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.88]) by smtp.gmail.com with ESMTPSA id m11sm34336122pgt.56.2018.01.11.02.12.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 02:12:50 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 17/26] KVM: PPC: Book3S PR: add math support for PR KVM HTM Date: Thu, 11 Jan 2018 18:11:30 +0800 Message-Id: <1515665499-31710-18-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> References: <1515665499-31710-1-git-send-email-wei.guo.simon@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Guo , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Simon Guo The math registers will be saved into vcpu->arch.fp/vr and corresponding vcpu->arch.fp_tm/vr_tm area. We flush or giveup the math regs into vcpu->arch.fp/vr before saving transaction. After transaction is restored, the math regs will be loaded back into regs. If there is a FP/VEC/VSX unavailable exception during transaction active state, the math checkpoint content might be incorrect and we need to do treclaim./load the correct checkpoint val/trechkpt. sequence to retry the transaction. If transaction is active, and the qemu process is switching out of CPU, we need to keep the "guest_owned_ext" bits unchanged after qemu process is switched back. The reason is that if we allow guest_owned_ext change freely during a transaction, there will lack information to handle FP/VEC/VSX unavailable exception during transaction active state. Detail is as follows: Assume we allow math bits to be given up freely during transaction: - If it is the first FP unavailable exception after tbegin., vcpu->arch.fp/ vr need to be loaded for trechkpt. - If it is the 2nd or subsequent FP unavailable exception after tbegin., vcpu->arch.fp_tm/vr_tm need to be loaded for trechkpt. It will bring much additional complexity to cover both cases. That is why we always save guest_owned_ext into vcpu->arch.save_msr_tm at kvmppc_save_tm_pr(), then check those bits in vcpu->arch.save_msr_tm at kvmppc_restore_tm_pr() to determine what math contents will be loaded. With this, we will always load vcpu->arch.fp/vr in math unavailable exception during active transaction. Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_host.h | 4 +- arch/powerpc/kvm/book3s_pr.c | 114 +++++++++++++++++++++++++++++------- 2 files changed, 95 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index eb3b821..1124c62 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -627,7 +627,9 @@ struct kvm_vcpu_arch { struct thread_vr_state vr_tm; u32 vrsave_tm; /* also USPRG0 */ - u64 save_msr_tm; /* TS bits: whether TM restore is required */ + u64 save_msr_tm; /* TS bits: whether TM restore is required + * FP/VEC/VSX bits: saved guest_owned_ext + */ #endif #ifdef CONFIG_KVM_EXIT_TIMING diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index eef0928..c35bd02 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -55,6 +55,7 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr); +static int kvmppc_load_ext(struct kvm_vcpu *vcpu, ulong msr); static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac); /* Some compatibility defines */ @@ -280,6 +281,33 @@ void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) return; } + /* when we are in transaction active state and switch out of CPU, + * we need to be careful to not "change" guest_owned_ext bits after + * kvmppc_save_tm_pr()/kvmppc_restore_tm_pr() pair. The reason is + * that we need to distinguish following 2 FP/VEC/VSX unavailable + * exception cases in TM active state: + * 1) tbegin. is executed with guest_owned_ext FP/VEC/VSX off. Then + * there comes a FP/VEC/VSX unavailable exception during transaction. + * In this case, the vcpu->arch.fp/vr contents need to be loaded as + * checkpoint contents. + * 2) tbegin. is executed with guest_owned_ext FP/VEC/VSX on. Then + * there is task switch during suspended state. If we giveup ext and + * update guest_owned_ext as no FP/VEC/VSX bits during context switch, + * we need to load vcpu->arch.fp_tm/vr_tm contents as checkpoint + * content. + * + * As a result, we don't change guest_owned_ext bits during + * kvmppc_save/restore_tm_pr() pair. So that we can only use + * vcpu->arch.fp/vr contents as checkpoint contents. + * And we need to "save" the guest_owned_ext bits here who indicates + * which math bits need to be "restored" in kvmppc_restore_tm_pr(). + */ + vcpu->arch.save_msr_tm &= ~(MSR_FP | MSR_VEC | MSR_VSX); + vcpu->arch.save_msr_tm |= (vcpu->arch.guest_owned_ext & + (MSR_FP | MSR_VEC | MSR_VSX)); + + kvmppc_giveup_ext(vcpu, MSR_VSX); + preempt_disable(); _kvmppc_save_tm_pr(vcpu, mfmsr()); preempt_enable(); @@ -295,6 +323,16 @@ void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) preempt_disable(); _kvmppc_restore_tm_pr(vcpu, vcpu->arch.save_msr_tm); preempt_enable(); + + if (vcpu->arch.save_msr_tm & MSR_VSX) + kvmppc_load_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); + else { + if (vcpu->arch.save_msr_tm & MSR_VEC) + kvmppc_load_ext(vcpu, MSR_VEC); + + if (vcpu->arch.save_msr_tm & MSR_FP) + kvmppc_load_ext(vcpu, MSR_FP); + } } #endif @@ -788,12 +826,41 @@ static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) #endif } +static int kvmppc_load_ext(struct kvm_vcpu *vcpu, ulong msr) +{ + struct thread_struct *t = ¤t->thread; + + if (msr & MSR_FP) { + preempt_disable(); + enable_kernel_fp(); + load_fp_state(&vcpu->arch.fp); + disable_kernel_fp(); + t->fp_save_area = &vcpu->arch.fp; + preempt_enable(); + } + + if (msr & MSR_VEC) { +#ifdef CONFIG_ALTIVEC + preempt_disable(); + enable_kernel_altivec(); + load_vr_state(&vcpu->arch.vr); + disable_kernel_altivec(); + t->vr_save_area = &vcpu->arch.vr; + preempt_enable(); +#endif + } + + t->regs->msr |= msr; + vcpu->arch.guest_owned_ext |= msr; + kvmppc_recalc_shadow_msr(vcpu); + + return RESUME_GUEST; +} + /* Handle external providers (FPU, Altivec, VSX) */ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, ulong msr) { - struct thread_struct *t = ¤t->thread; - /* When we have paired singles, we emulate in software */ if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) return RESUME_GUEST; @@ -829,31 +896,34 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, printk(KERN_INFO "Loading up ext 0x%lx\n", msr); #endif - if (msr & MSR_FP) { +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* if TM is active, the checkpointed math content + * might be invalid. We need to reclaim current + * transaction, load the correct math, and perform + * rechkpoint. + */ + if (MSR_TM_ACTIVE(mfmsr())) { preempt_disable(); - enable_kernel_fp(); - load_fp_state(&vcpu->arch.fp); - disable_kernel_fp(); - t->fp_save_area = &vcpu->arch.fp; - preempt_enable(); - } + kvmppc_save_tm_pr(vcpu); + /* need update the chkpt math reg saving content, + * so that we can checkpoint with desired fp value. + */ + if (msr & MSR_FP) + memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp, + sizeof(struct thread_fp_state)); + + if (msr & MSR_VEC) { + memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr, + sizeof(struct thread_vr_state)); + vcpu->arch.vrsave_tm = vcpu->arch.vrsave; + } - if (msr & MSR_VEC) { -#ifdef CONFIG_ALTIVEC - preempt_disable(); - enable_kernel_altivec(); - load_vr_state(&vcpu->arch.vr); - disable_kernel_altivec(); - t->vr_save_area = &vcpu->arch.vr; + kvmppc_restore_tm_pr(vcpu); preempt_enable(); -#endif } +#endif - t->regs->msr |= msr; - vcpu->arch.guest_owned_ext |= msr; - kvmppc_recalc_shadow_msr(vcpu); - - return RESUME_GUEST; + return kvmppc_load_ext(vcpu, msr); } /*