From patchwork Tue Dec 19 17:27:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lombard X-Patchwork-Id: 850985 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3z1Qm26H4Nz9t2W for ; Wed, 20 Dec 2017 05:04:50 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3z1Qm23C6VzDrXQ for ; Wed, 20 Dec 2017 05:04:50 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=clombard@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3z1Px03rRLzDrYY for ; Wed, 20 Dec 2017 04:27:31 +1100 (AEDT) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vBJHOwkM071427 for ; Tue, 19 Dec 2017 12:27:27 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ey4ckj390-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 19 Dec 2017 12:27:26 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 19 Dec 2017 17:27:20 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vBJHRJYu42729474; Tue, 19 Dec 2017 17:27:19 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 08A4A42047; Tue, 19 Dec 2017 17:21:26 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C329142042; Tue, 19 Dec 2017 17:21:25 +0000 (GMT) Received: from lombard-w520.nice-meridia.fr.ibm.com (unknown [9.134.171.23]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 19 Dec 2017 17:21:25 +0000 (GMT) From: Christophe Lombard To: linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, vaibhav@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com Subject: [PATCH V4] cxl: Add support for ASB_Notify on POWER9 Date: Tue, 19 Dec 2017 18:27:18 +0100 X-Mailer: git-send-email 2.7.4 X-TM-AS-GCONF: 00 x-cbid: 17121917-0016-0000-0000-0000050EDA03 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17121917-0017-0000-0000-0000284B02E8 Message-Id: <1513704438-28958-1-git-send-email-clombard@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-12-19_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1712190248 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The POWER9 core supports a new feature: ASB_Notify which requires the support of the Special Purpose Register: TIDR. The ASB_Notify command, generated by the AFU, will attempt to wake-up the host thread identified by the particular LPID:PID:TID. This patch assign a unique TIDR (thread id) for the current thread which will be used in the process element entry. A next patch will handle a new kind of "compatible" property in the device-tree (PHB DT node) indicating which version of CAPI and which features are supported, instead of handling PVR values. Signed-off-by: Christophe Lombard Reviewed-by: Philippe Bergheaud --- Changelog[v4] - Rebased to latest upstream. - Updated the ioctl interface. - Removed the field tid in the context structure. Changelog[v3] - Rebased to latest upstream. - Updated attr->tid field in cxllib_get_PE_attributes(). Changelog[v2] - Rebased to latest upstream. - Updated the ioctl interface. - Added a checking to allow updating the TIDR if a P9 chip is present. --- arch/powerpc/kernel/process.c | 1 + drivers/misc/cxl/context.c | 15 +++++++++++++++ drivers/misc/cxl/cxl.h | 3 +++ drivers/misc/cxl/cxllib.c | 3 ++- drivers/misc/cxl/file.c | 7 +++++++ drivers/misc/cxl/native.c | 2 +- include/uapi/misc/cxl.h | 4 +++- 7 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 5acb5a1..a6a70e2 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1589,6 +1589,7 @@ int set_thread_tidr(struct task_struct *t) return 0; } +EXPORT_SYMBOL_GPL(set_thread_tidr); #endif /* CONFIG_PPC64 */ diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c index 12a41b2..e309d35 100644 --- a/drivers/misc/cxl/context.c +++ b/drivers/misc/cxl/context.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "cxl.h" @@ -362,3 +363,17 @@ void cxl_context_mm_count_put(struct cxl_context *ctx) if (ctx->mm) mmdrop(ctx->mm); } + +int cxl_context_thread_tidr(struct cxl_context *ctx) +{ + int rc = 0; + + if (!cxl_is_power9()) + return -ENODEV; + + rc = set_thread_tidr(current); + pr_devel("%s: current tidr: %ld\n", __func__, + current->thread.tidr); + + return rc; +} diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h index e46a406..1a5db0b 100644 --- a/drivers/misc/cxl/cxl.h +++ b/drivers/misc/cxl/cxl.h @@ -1169,4 +1169,7 @@ void cxl_context_mm_count_get(struct cxl_context *ctx); /* Decrements the reference count to "struct mm_struct" */ void cxl_context_mm_count_put(struct cxl_context *ctx); +/* Handles an unique TIDR (thread id) for the current thread */ +int cxl_context_thread_tidr(struct cxl_context *ctx); + #endif diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c index dc9bc18..30ccba4 100644 --- a/drivers/misc/cxl/cxllib.c +++ b/drivers/misc/cxl/cxllib.c @@ -199,10 +199,11 @@ int cxllib_get_PE_attributes(struct task_struct *task, */ attr->pid = mm->context.id; mmput(mm); + attr->tid = task->thread.tidr; } else { attr->pid = 0; + attr->tid = 0; } - attr->tid = 0; return 0; } EXPORT_SYMBOL_GPL(cxllib_get_PE_attributes); diff --git a/drivers/misc/cxl/file.c b/drivers/misc/cxl/file.c index 76c0b0c..a823c76 100644 --- a/drivers/misc/cxl/file.c +++ b/drivers/misc/cxl/file.c @@ -248,6 +248,13 @@ static long afu_ioctl_start_work(struct cxl_context *ctx, */ smp_mb(); + /* Assign a unique TIDR (thread id) for the current thread */ + if (work.flags & CXL_START_WORK_TID) { + rc = cxl_context_thread_tidr(ctx); + if (rc) + goto out; + } + trace_cxl_attach(ctx, work.work_element_descriptor, work.num_interrupts, amr); if ((rc = cxl_ops->attach_process(ctx, false, work.work_element_descriptor, diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c index 02b6b45..036fe5b 100644 --- a/drivers/misc/cxl/native.c +++ b/drivers/misc/cxl/native.c @@ -673,7 +673,7 @@ static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr) pid = ctx->mm->context.id; } - ctx->elem->common.tid = 0; + ctx->elem->common.tid = cpu_to_be32(current->thread.tidr); ctx->elem->common.pid = cpu_to_be32(pid); ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); diff --git a/include/uapi/misc/cxl.h b/include/uapi/misc/cxl.h index 49e8fd0..980ee8f 100644 --- a/include/uapi/misc/cxl.h +++ b/include/uapi/misc/cxl.h @@ -31,9 +31,11 @@ struct cxl_ioctl_start_work { #define CXL_START_WORK_AMR 0x0000000000000001ULL #define CXL_START_WORK_NUM_IRQS 0x0000000000000002ULL #define CXL_START_WORK_ERR_FF 0x0000000000000004ULL +#define CXL_START_WORK_TID 0x0000000000000008ULL #define CXL_START_WORK_ALL (CXL_START_WORK_AMR |\ CXL_START_WORK_NUM_IRQS |\ - CXL_START_WORK_ERR_FF) + CXL_START_WORK_ERR_FF |\ + CXL_START_WORK_TID) /* Possible modes that an afu can be in */