From patchwork Wed Aug 30 04:12:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Mackerras X-Patchwork-Id: 807403 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xht2k4z9kz9s9Y for ; Wed, 30 Aug 2017 14:34:54 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.b="XWSl+vTo"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xht2k3Xb0zDqLw for ; Wed, 30 Aug 2017 14:34:54 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.b="XWSl+vTo"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYJ22PXzDqGV for ; Wed, 30 Aug 2017 14:12:52 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.b="XWSl+vTo"; dkim-atps=neutral Received: by ozlabs.org (Postfix) id 3xhsYJ0lJDz9sQl; Wed, 30 Aug 2017 14:12:52 +1000 (AEST) Delivered-To: linuxppc-dev@ozlabs.org Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPSA id 3xhsYH6Ssqz9sP5 for ; Wed, 30 Aug 2017 14:12:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1504066371; bh=qiMi7qPp9GxgZMSpn2EFGV64Z45QfWyKG3dMMQZHeXw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=XWSl+vToM5QKjTnB/225QycOCPgLpBPcNvyYq+77CD2fiTjOLuHHzlKn6bpzQ7wx3 qlj45ntxUKAr468fbAl4vT0ltHjlybSaxgUzS2weuBWd+c/rwLfYvoalULQjH66w3Z JM9s8ueirADDcIJf3iPdKJ+ORg7xU4xA5h6O4QwZiK1nvnUkFsBE9ZY5JfnDXzvRuu fuXNFYzhhbuPNNlSgGFs+vjA9atkGtsZ6Hk8y6S/BxDPsg8+ni8gWlVjqfNpOuQP5x OAMuZeLsSdRYDu5ecA4WOqTS/t31t57bjuNAsUZXIVxUhIn2oLumfTI+lK6anVDM1j En57franpqO+Q== From: Paul Mackerras To: linuxppc-dev@ozlabs.org Subject: [PATCH v3 11/17] powerpc: Emulate vector element load/store instructions Date: Wed, 30 Aug 2017 14:12:34 +1000 Message-Id: <1504066360-30128-12-git-send-email-paulus@ozlabs.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504066360-30128-1-git-send-email-paulus@ozlabs.org> References: <1504066360-30128-1-git-send-email-paulus@ozlabs.org> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This adds code to analyse_instr() and emulate_step() to handle the vector element loads and stores: lvebx, lvehx, lvewx, stvebx, stvehx, stvewx. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/sstep.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 91ae031..167d40d 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -476,7 +476,7 @@ static nokprobe_inline int do_vec_load(int rn, unsigned long ea, return -EFAULT; /* align to multiple of size */ ea &= ~(size - 1); - err = copy_mem_in(u.b, ea, size); + err = copy_mem_in(&u.b[ea & 0xf], ea, size); if (err) return err; @@ -508,7 +508,7 @@ static nokprobe_inline int do_vec_store(int rn, unsigned long ea, else u.v = current->thread.vr_state.vr[rn]; preempt_enable(); - return copy_mem_out(u.b, ea, size); + return copy_mem_out(&u.b[ea & 0xf], ea, size); } #endif /* CONFIG_ALTIVEC */ @@ -1807,12 +1807,46 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, break; #ifdef CONFIG_ALTIVEC + /* + * Note: for the load/store vector element instructions, + * bits of the EA say which field of the VMX register to use. + */ + case 7: /* lvebx */ + op->type = MKOP(LOAD_VMX, 0, 1); + op->element_size = 1; + break; + + case 39: /* lvehx */ + op->type = MKOP(LOAD_VMX, 0, 2); + op->element_size = 2; + break; + + case 71: /* lvewx */ + op->type = MKOP(LOAD_VMX, 0, 4); + op->element_size = 4; + break; + case 103: /* lvx */ case 359: /* lvxl */ op->type = MKOP(LOAD_VMX, 0, 16); op->element_size = 16; break; + case 135: /* stvebx */ + op->type = MKOP(STORE_VMX, 0, 1); + op->element_size = 1; + break; + + case 167: /* stvehx */ + op->type = MKOP(STORE_VMX, 0, 2); + op->element_size = 2; + break; + + case 199: /* stvewx */ + op->type = MKOP(STORE_VMX, 0, 4); + op->element_size = 4; + break; + case 231: /* stvx */ case 487: /* stvxl */ op->type = MKOP(STORE_VMX, 0, 16);