From patchwork Wed Jun 28 18:57:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anju T Sudhakar X-Patchwork-Id: 781851 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyXFT6xW5z9s72 for ; Thu, 29 Jun 2017 05:01:17 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wyXFT69cczDr4w for ; Thu, 29 Jun 2017 05:01:17 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wyX9C1T4QzDr1h for ; Thu, 29 Jun 2017 04:57:35 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v5SIs9ns139690 for ; Wed, 28 Jun 2017 14:57:33 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0a-001b2d01.pphosted.com with ESMTP id 2bcgk7cc8n-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 28 Jun 2017 14:57:32 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 29 Jun 2017 04:57:28 +1000 Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v5SIvSw52032030 for ; Thu, 29 Jun 2017 04:57:28 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v5SIvJ1V029489 for ; Thu, 29 Jun 2017 04:57:20 +1000 Received: from xenial-xerus.in.ibm.com ([9.79.214.156]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v5SIv9Td029282; Thu, 29 Jun 2017 04:57:15 +1000 From: Anju T Sudhakar To: mpe@ellerman.id.au Subject: [PATCH v11 01/10] powerpc/powernv: Data structure and macros definitions for IMC Date: Thu, 29 Jun 2017 00:27:06 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498676232-23841-1-git-send-email-anju@linux.vnet.ibm.com> References: <1498676232-23841-1-git-send-email-anju@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17062818-0048-0000-0000-0000024BDE91 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17062818-0049-0000-0000-000047FCC2CE Message-Id: <1498676232-23841-2-git-send-email-anju@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-28_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706280300 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com, ego@linux.vnet.ibm.com, mikey@neuling.org, maddy@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, eranian@google.com, anju@linux.vnet.ibm.com, anton@samba.org, sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, dja@axtens.net Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Madhavan Srinivasan Create a new header file to add the data structures and macros needed for In-Memory Collection (IMC) counter support. Signed-off-by: Anju T Sudhakar Signed-off-by: Hemant Kumar Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/imc-pmu.h | 99 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 arch/powerpc/include/asm/imc-pmu.h diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h new file mode 100644 index 0000000..ffaea0b --- /dev/null +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -0,0 +1,99 @@ +#ifndef PPC_POWERNV_IMC_PMU_DEF_H +#define PPC_POWERNV_IMC_PMU_DEF_H + +/* + * IMC Nest Performance Monitor counter support. + * + * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. + * (C) 2017 Anju T Sudhakar, IBM Corporation. + * (C) 2017 Hemant K Shaw, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or later version. + */ + +#include +#include +#include +#include +#include + +/* + * For static allocation of some of the structures. + */ +#define IMC_MAX_PMUS 32 + +/* + * This macro is used for memory buffer allocation of + * event names and event string + */ +#define IMC_MAX_NAME_VAL_LEN 96 + +/* + * Currently Microcode supports a max of 256KB of counter memory + * in the reserved memory region. Max pages to mmap (considering 4K PAGESIZE). + */ +#define IMC_MAX_PAGES 64 + +/* + *Compatbility macros for IMC devices + */ +#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" +#define IMC_DTB_UNIT_COMPAT "ibm,imc-counters" + +/* + * Structure to hold memory address information for imc units. + */ +struct imc_mem_info { + u32 id; + u64 *vbase[IMC_MAX_PAGES]; +}; + +/* + * Place holder for nest pmu events and values. + */ +struct imc_events { + char *ev_name; + char *ev_value; +}; + +#define IMC_FORMAT_ATTR 0 +#define IMC_CPUMASK_ATTR 1 +#define IMC_EVENT_ATTR 2 +#define IMC_NULL_ATTR 3 + +/* + * Device tree parser code detects IMC pmu support and + * registers new IMC pmus. This structure will hold the + * pmu functions, events, counter memory information + * and attrs for each imc pmu and will be referenced at + * the time of pmu registration. + */ +struct imc_pmu { + struct pmu pmu; + int domain; + /* + * flag to notify whether the memory is mmaped + * or allocated by kernel. + */ + int imc_counter_mmaped; + struct imc_mem_info *mem_info; + struct imc_events *events; + u32 counter_mem_size; + /* + * Attribute groups for the PMU. Slot 0 used for + * format attribute, slot 1 used for cpusmask attribute, + * slot 2 used for event attribute. Slot 3 keep as + * NULL. + */ + const struct attribute_group *attr_groups[4]; +}; + +/* + * Domains for IMC PMUs + */ +#define IMC_DOMAIN_NEST 1 + +#endif /* PPC_POWERNV_IMC_PMU_DEF_H */