From patchwork Thu Jan 26 01:38:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukadev Bhattiprolu X-Patchwork-Id: 719941 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v84S913FLz9t0v for ; Thu, 26 Jan 2017 12:43:05 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3v84S9036qzDqLP for ; Thu, 26 Jan 2017 12:43:05 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3v84M55PLvzDq5s for ; Thu, 26 Jan 2017 12:38:41 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 3v84M54sHzz9t1C; Thu, 26 Jan 2017 12:38:41 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v84M52KTNz9t14 for ; Thu, 26 Jan 2017 12:38:41 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v0Q1cVK7123120 for ; Wed, 25 Jan 2017 20:38:39 -0500 Received: from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158]) by mx0a-001b2d01.pphosted.com with ESMTP id 2870k3x6pa-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 25 Jan 2017 20:38:39 -0500 Received: from localhost by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 25 Jan 2017 18:38:34 -0700 Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 2407C19D8026; Wed, 25 Jan 2017 18:37:49 -0700 (MST) Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v0Q1cNqo16777668; Thu, 26 Jan 2017 01:38:23 GMT Received: from localhost (unknown [127.0.0.1]) by IMSVA (Postfix) with SMTP id C49F311204B; Wed, 25 Jan 2017 20:38:23 -0500 (EST) X-IMSS-HAND-OFF-DIRECTIVE: 127.0.0.1:10026 Received: from suka-w540.usor.ibm.com (unknown [9.70.94.25]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP id AAFDD11204B; Wed, 25 Jan 2017 20:38:21 -0500 (EST) From: Sukadev Bhattiprolu To: Michael Ellerman Subject: [PATCH v2 04/10] VAS: Define helpers for access MMIO regions Date: Wed, 25 Jan 2017 17:38:02 -0800 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1485394688-31129-1-git-send-email-sukadev@linux.vnet.ibm.com> References: <1485394688-31129-1-git-send-email-sukadev@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17012601-0024-0000-0000-000015CCEFE8 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006499; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000200; SDB=6.00812736; UDB=6.00396398; IPR=6.00590154; BA=6.00005090; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014050; XFM=3.00000011; UTC=2017-01-26 01:38:36 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17012601-0025-0000-0000-0000484435C6 Message-Id: <1485394688-31129-5-git-send-email-sukadev@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-25_18:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701260014 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com, linuxppc-dev@ozlabs.org, apopple@au1.ibm.com, oohall@gmail.com, michael.neuling@au1.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Define some helper functions to access the MMIO regions. We use these in a follow-on patches to read/write VAS hardware registers. These helpers are also used to later issue 'paste' instructions to submit requests to the NX hardware engines. Signed-off-by: Sukadev Bhattiprolu Changelog [v2]: - Get HVWC, UWC and paste addresses from window->vinst (i.e DT) rather than kernel macros. --- drivers/misc/vas/vas-window.c | 112 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/misc/vas/vas-window.c b/drivers/misc/vas/vas-window.c index 468f3bf..cfbd2f4 100644 --- a/drivers/misc/vas/vas-window.c +++ b/drivers/misc/vas/vas-window.c @@ -9,9 +9,121 @@ #include #include +#include +#include #include #include "vas-internal.h" +/* + * Compute the paste address region for the window @window using the + * ->win_base_addr and ->win_id_shift we got from device tree. + */ +void compute_paste_address(struct vas_window *window, uint64_t *addr, int *len) +{ + uint64_t base, shift; + int winid; + + base = window->vinst->win_base_addr; + shift = window->vinst->win_id_shift; + winid = window->winid; + + *addr = base + (winid << shift); + *len = PAGE_SIZE; + + pr_debug("Txwin #%d: Paste addr 0x%llx\n", winid, *addr); +} + +static inline void get_hvwc_mmio_bar(struct vas_window *window, + uint64_t *start, int *len) +{ + uint64_t pbaddr; + + pbaddr = window->vinst->hvwc_bar_start; + *start = pbaddr + window->winid * VAS_HVWC_SIZE; + *len = VAS_HVWC_SIZE; +} + +static inline void get_uwc_mmio_bar(struct vas_window *window, + uint64_t *start, int *len) +{ + uint64_t pbaddr; + + pbaddr = window->vinst->uwc_bar_start; + *start = pbaddr + window->winid * VAS_UWC_SIZE; + *len = VAS_UWC_SIZE; +} + +static void *map_mmio_region(char *name, uint64_t start, int len) +{ + void *map; + + if (!request_mem_region(start, len, name)) { + pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n", + __func__, start, len); + return NULL; + } + + map = __ioremap(start, len, pgprot_val(pgprot_cached(__pgprot(0)))); + if (!map) { + pr_devel("%s(): ioremap(0x%llx, %d) failed\n", __func__, start, + len); + return NULL; + } + + return map; +} + +/* + * Unmap the MMIO regions for a window. + */ +void unmap_wc_mmio_bars(struct vas_window *window) +{ + int len; + uint64_t busaddr_start; + + if (window->paste_kaddr) { + iounmap(window->paste_kaddr); + compute_paste_address(window, &busaddr_start, &len); + release_mem_region((phys_addr_t)busaddr_start, len); + } + + if (window->hvwc_map) { + iounmap(window->hvwc_map); + get_hvwc_mmio_bar(window, &busaddr_start, &len); + release_mem_region((phys_addr_t)busaddr_start, len); + } + + if (window->uwc_map) { + iounmap(window->uwc_map); + get_uwc_mmio_bar(window, &busaddr_start, &len); + release_mem_region((phys_addr_t)busaddr_start, len); + } +} + +/* + * Find the Hypervisor Window Context (HVWC) MMIO Base Address Region and the + * OS/User Window Context (UWC) MMIO Base Address Region for the given window. + * Map these bus addresses and save the mapped kernel addresses in @window. + */ +int map_wc_mmio_bars(struct vas_window *window) +{ + int len; + uint64_t start; + + window->hvwc_map = window->uwc_map = NULL; + + get_hvwc_mmio_bar(window, &start, &len); + window->hvwc_map = map_mmio_region("HVWCM_Window", start, len); + + get_uwc_mmio_bar(window, &start, &len); + window->uwc_map = map_mmio_region("UWCM_Window", start, len); + + if (!window->hvwc_map || !window->uwc_map) + return -1; + + return 0; +} + /* stub for now */ int vas_window_reset(struct vas_instance *vinst, int winid) {