@@ -167,7 +167,8 @@
#define OPAL_INT_EOI 124
#define OPAL_INT_SET_MFRR 125
#define OPAL_PCI_TCE_KILL 126
-#define OPAL_LAST 126
+#define OPAL_VAS_READ_FIR 128
+#define OPAL_LAST 128
/* Device tree flags */
@@ -228,6 +228,7 @@ int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
int64_t opal_rm_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
uint32_t pe_num, uint32_t tce_size,
uint64_t dma_addr, uint32_t npages);
+int64_t opal_vas_read_fir(uint32_t chip_id, int32_t idx, __be64 *fir);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
@@ -131,4 +131,9 @@ extern int vas_copy_crb(void *crb, int offset, bool first);
*/
extern int vas_paste_crb(struct vas_window *win, int off, bool last, bool re);
+/*
+ * Print the VAS Fault Isolation Registers (FIR) for the chip @chip.
+ * Used when we encounter an error/exception in VAS.
+ */
+void vas_print_regs(int chip);
#endif
@@ -62,6 +62,7 @@
#include <linux/kprobes.h>
#include <linux/kdebug.h>
+#include <asm/vas.h>
/* Transactional Memory debug */
#ifdef TM_DEBUG_SW
@@ -1339,6 +1340,8 @@ void show_regs(struct pt_regs * regs)
break;
}
printk("\n");
+
+ vas_print_regs(0);
#ifdef CONFIG_KALLSYMS
/*
* Lookup NIP late so we have the best change of getting the
@@ -308,3 +308,4 @@ OPAL_CALL(opal_int_eoi, OPAL_INT_EOI);
OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR);
OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL);
OPAL_CALL_REAL(opal_rm_pci_tce_kill, OPAL_PCI_TCE_KILL);
+OPAL_CALL(opal_vas_read_fir, OPAL_VAS_READ_FIR);
@@ -15,10 +15,48 @@
#include <linux/io.h>
#include <asm/vas.h>
#include "vas-internal.h"
+#include <asm/opal-api.h>
+#include <asm/opal.h>
int vas_initialized;
struct vas_instance *vas_instances;
+/*
+ * Read the Fault Isolation Registers (FIR) from skiboot into @fir.
+ */
+static void read_fault_regs(int chip, uint64_t *fir)
+{
+ int i;
+ int64_t rc;
+
+ for (i = 0; i < 8; i++)
+ rc = opal_vas_read_fir(chip, i, &fir[i]);
+}
+
+/*
+ * Print the VAS Fault Isolation Registers (FIR) for the chip @chip.
+ * Used when we encounter an error/exception in VAS.
+ *
+ * TODO: Find the chip id where the exception occurred. Hard coding to
+ * chip 0 for now.
+ */
+void vas_print_regs(int chip)
+{
+ int i;
+ uint64_t firs[8];
+
+ /* TODO: Only dump FIRs for first chip for now */
+ if (chip == -1)
+ chip = 0;
+
+ read_fault_regs(chip, firs);
+ for (i = 0; i < 8; i += 4) {
+ pr_err("FIR%d: 0x%llx 0x%llx 0x%llx 0x%llx\n", i,
+ firs[i], firs[i+1], firs[i+2], firs[i+3]);
+ }
+}
+
+
static void init_vas_chip(struct vas_instance *vinst)
{
int i;
Define an interface to read and print the VAS error/debug registers. Currently this interface only prints the Fault Isolation Registers (FIR). It needs to make OPAL call(s) to read the registers since they are only available via the SCOM interface. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> --- arch/powerpc/include/asm/opal-api.h | 3 +- arch/powerpc/include/asm/opal.h | 1 + arch/powerpc/include/asm/vas.h | 5 ++++ arch/powerpc/kernel/process.c | 3 ++ arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + drivers/misc/vas/vas.c | 38 ++++++++++++++++++++++++++ 6 files changed, 50 insertions(+), 1 deletion(-)