@@ -261,3 +261,21 @@ void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[])
if (pmc <= 3)
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
}
+
+void isa207_get_arch_regs(struct perf_arch_regs *regs)
+{
+ regs->regs[PERF_ARCH_REG_POWERPC_PVR] = mfspr(SPRN_PVR);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC1] = mfspr(SPRN_PMC1);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC2] = mfspr(SPRN_PMC2);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC3] = mfspr(SPRN_PMC3);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC4] = mfspr(SPRN_PMC4);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC5] = mfspr(SPRN_PMC5);
+ regs->regs[PERF_ARCH_REG_POWERPC_PMC6] = mfspr(SPRN_PMC6);
+ regs->regs[PERF_ARCH_REG_POWERPC_MMCR0] = mfspr(SPRN_MMCR0);
+ regs->regs[PERF_ARCH_REG_POWERPC_MMCR1] = mfspr(SPRN_MMCR1);
+ regs->regs[PERF_ARCH_REG_POWERPC_SIER] = mfspr(SPRN_SIER);
+ regs->regs[PERF_ARCH_REG_POWERPC_SIAR] = mfspr(SPRN_SIAR);
+ regs->regs[PERF_ARCH_REG_POWERPC_SDAR] = mfspr(SPRN_SDAR);
+ regs->regs[PERF_ARCH_REG_POWERPC_MMCRA] = mfspr(SPRN_MMCRA);
+ regs->regs[PERF_ARCH_REG_POWERPC_MMCR2] = mfspr(SPRN_MMCR2);
+}
@@ -16,6 +16,7 @@
#include <linux/perf_event.h>
#include <asm/firmware.h>
#include <asm/cputable.h>
+#include <uapi/asm/perf_regs.h>
/*
* Raw event encoding for PowerISA v2.07:
@@ -227,10 +228,19 @@
#define MAX_ALT 2
#define MAX_PMU_COUNTERS 6
+#define ISA207_ARCH_REGS_MASK (PERF_ARCH_REG_PVR |\
+ PERF_ARCH_REG_PMC1 | PERF_ARCH_REG_PMC2 |\
+ PERF_ARCH_REG_PMC3 | PERF_ARCH_REG_PMC4 |\
+ PERF_ARCH_REG_PMC5 | PERF_ARCH_REG_PMC6 |\
+ PERF_ARCH_REG_MMCR0 | PERF_ARCH_REG_MMCR1 |\
+ PERF_ARCH_REG_SIER | PERF_ARCH_REG_SIAR |\
+ PERF_ARCH_REG_SDAR | PERF_ARCH_REG_MMCRA | PERF_ARCH_REG_MMCR2)
+
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
int isa207_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], unsigned long mmcr[],
struct perf_event *pevents[]);
void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]);
+void isa207_get_arch_regs(struct perf_arch_regs *regs);
#endif
@@ -394,6 +394,8 @@ static struct power_pmu power8_pmu = {
.cache_events = &power8_cache_events,
.attr_groups = power8_pmu_attr_groups,
.bhrb_nr = 32,
+ .ar_mask = ISA207_ARCH_REGS_MASK,
+ .get_arch_regs = isa207_get_arch_regs,
};
static int __init init_power8_pmu(void)
@@ -307,6 +307,8 @@ static struct power_pmu power9_pmu = {
.cache_events = &power9_cache_events,
.attr_groups = power9_pmu_attr_groups,
.bhrb_nr = 32,
+ .ar_mask = ISA207_ARCH_REGS_MASK,
+ .get_arch_regs = isa207_get_arch_regs,
};
static int __init init_power9_pmu(void)
Add code to define support functions and registers mask for Power8 and later processor. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Stephane Eranian <eranian@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> --- arch/powerpc/perf/isa207-common.c | 18 ++++++++++++++++++ arch/powerpc/perf/isa207-common.h | 10 ++++++++++ arch/powerpc/perf/power8-pmu.c | 2 ++ arch/powerpc/perf/power9-pmu.c | 2 ++ 4 files changed, 32 insertions(+)