diff --git a/tools/perf/arch/powerpc/util/power7-events.h b/tools/perf/arch/powerpc/util/power7-events.h
new file mode 100644
index 0000000..a2f928b
--- /dev/null
+++ b/tools/perf/arch/powerpc/util/power7-events.h
@@ -0,0 +1,3315 @@
+#ifndef __POWER7_EVENTS_H__
+#define __POWER7_EVENTS_H__
+
+/*
+* File:    power7_events.h
+* CVS:
+* Author:  Corey Ashford
+*          cjashfor@us.ibm.com
+* Mods:    Sukadev Bhattiprolu
+*          sukadev@linux.vnet.ibm.com
+* Mods:    <your name here>
+*          <your email address>
+*
+* (C) Copyright IBM Corporation, 2009.  All Rights Reserved.
+* Contributed by Corey Ashford <cjashfor.ibm.com>
+*
+* Note: This code was generated based on power7-events.h in libpfm4
+*
+* Documentation on the PMU events can be found at:
+*  http://www.power.org/documentation/comprehensive-pmu-event-reference-power7
+*/
+
+static const struct perf_pmu_event power7_pmu_events[] = {
+{
+	.name = "PM_IC_DEMAND_L2_BR_ALL",
+	.code = 0x4898,
+	.short_desc = " L2 I cache demand request due to BHT or redirect",
+	.long_desc = " L2 I cache demand request due to BHT or redirect",
+},
+{
+	.name = "PM_GCT_UTIL_7_TO_10_SLOTS",
+	.code = 0x20a0,
+	.short_desc = "GCT Utilization 7-10 entries",
+	.long_desc = "GCT Utilization 7-10 entries",
+},
+{
+	.name = "PM_PMC2_SAVED",
+	.code = 0x10022,
+	.short_desc = "PMC2 Rewind Value saved",
+	.long_desc = "PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
+},
+{
+	.name = "PM_CMPLU_STALL_DFU",
+	.code = 0x2003c,
+	.short_desc = "Completion stall caused by Decimal Floating Point Unit",
+	.long_desc = "Completion stall caused by Decimal Floating Point Unit",
+},
+{
+	.name = "PM_VSU0_16FLOP",
+	.code = 0xa0a4,
+	.short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)  ",
+	.long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)  ",
+},
+{
+	.name = "PM_MRK_LSU_DERAT_MISS",
+	.code = 0x3d05a,
+	.short_desc = "Marked DERAT Miss",
+	.long_desc = "Marked DERAT Miss",
+},
+{
+	.name = "PM_MRK_ST_CMPL",
+	.code = 0x10034,
+	.short_desc = "marked  store finished (was complete)",
+	.long_desc = "A sampled store has completed (data home)",
+},
+{
+	.name = "PM_NEST_PAIR3_ADD",
+	.code = 0x40881,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD",
+},
+{
+	.name = "PM_L2_ST_DISP",
+	.code = 0x46180,
+	.short_desc = "All successful store dispatches",
+	.long_desc = "All successful store dispatches",
+},
+{
+	.name = "PM_L2_CASTOUT_MOD",
+	.code = 0x16180,
+	.short_desc = "L2 Castouts - Modified (M, Mu, Me)",
+	.long_desc = "An L2 line in the Modified state was castout. Total for all slices.",
+},
+{
+	.name = "PM_ISEG",
+	.code = 0x20a4,
+	.short_desc = "ISEG Exception",
+	.long_desc = "ISEG Exception",
+},
+{
+	.name = "PM_MRK_INST_TIMEO",
+	.code = 0x40034,
+	.short_desc = "marked Instruction finish timeout ",
+	.long_desc = "The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.",
+},
+{
+	.name = "PM_L2_RCST_DISP_FAIL_ADDR",
+	.code = 0x36282,
+	.short_desc = " L2  RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+	.long_desc = " L2  RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+},
+{
+	.name = "PM_LSU1_DC_PREF_STREAM_CONFIRM",
+	.code = 0xd0b6,
+	.short_desc = "LS1 'Dcache prefetch stream confirmed",
+	.long_desc = "LS1 'Dcache prefetch stream confirmed",
+},
+{
+	.name = "PM_IERAT_WR_64K",
+	.code = 0x40be,
+	.short_desc = "large page 64k ",
+	.long_desc = "large page 64k ",
+},
+{
+	.name = "PM_MRK_DTLB_MISS_16M",
+	.code = 0x4d05e,
+	.short_desc = "Marked Data TLB misses for 16M page",
+	.long_desc = "Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_IERAT_MISS",
+	.code = 0x100f6,
+	.short_desc = "IERAT Miss (Not implemented as DI on POWER6)",
+	.long_desc = "A translation request missed the Instruction Effective to Real Address Translation (ERAT) table",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_LMEM",
+	.code = 0x4d052,
+	.short_desc = "Marked PTEG loaded from local memory",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.",
+},
+{
+	.name = "PM_FLOP",
+	.code = 0x100f4,
+	.short_desc = "Floating Point Operation Finished",
+	.long_desc = "A floating point operation has completed",
+},
+{
+	.name = "PM_THRD_PRIO_4_5_CYC",
+	.code = 0x40b4,
+	.short_desc = " Cycles thread running at priority level 4 or 5",
+	.long_desc = " Cycles thread running at priority level 4 or 5",
+},
+{
+	.name = "PM_BR_PRED_TA",
+	.code = 0x40aa,
+	.short_desc = "Branch predict - target address",
+	.long_desc = "The target address of a branch instruction was predicted.",
+},
+{
+	.name = "PM_CMPLU_STALL_FXU",
+	.code = 0x20014,
+	.short_desc = "Completion stall caused by FXU instruction",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.",
+},
+{
+	.name = "PM_EXT_INT",
+	.code = 0x200f8,
+	.short_desc = "external interrupt",
+	.long_desc = "An interrupt due to an external exception occurred",
+},
+{
+	.name = "PM_VSU_FSQRT_FDIV",
+	.code = 0xa888,
+	.short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
+	.long_desc = "DP vector versions of fdiv,fsqrt ",
+},
+{
+	.name = "PM_MRK_LD_MISS_EXPOSED_CYC",
+	.code = 0x1003e,
+	.short_desc = "Marked Load exposed Miss ",
+	.long_desc = "Marked Load exposed Miss ",
+},
+{
+	.name = "PM_LSU1_LDF",
+	.code = 0xc086,
+	.short_desc = "LS1  Scalar Loads ",
+	.long_desc = "A floating point load was executed by LSU1",
+},
+{
+	.name = "PM_IC_WRITE_ALL",
+	.code = 0x488c,
+	.short_desc = "Icache sectors written, prefetch + demand",
+	.long_desc = "Icache sectors written, prefetch + demand",
+},
+{
+	.name = "PM_LSU0_SRQ_STFWD",
+	.code = 0xc0a0,
+	.short_desc = "LS0 SRQ forwarded data to a load",
+	.long_desc = "Data from a store instruction was forwarded to a load on unit 0.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+},
+{
+	.name = "PM_PTEG_FROM_RL2L3_MOD",
+	.code = 0x1c052,
+	.short_desc = "PTEG loaded from remote L2 or L3 modified",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a remote module due to a demand load or store.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L31_SHR",
+	.code = 0x1d04e,
+	.short_desc = "Marked data loaded from another L3 on same chip shared",
+	.long_desc = "Marked data loaded from another L3 on same chip shared",
+},
+{
+	.name = "PM_DATA_FROM_L21_MOD",
+	.code = 0x3c046,
+	.short_desc = "Data loaded from another L2 on same chip modified",
+	.long_desc = "Data loaded from another L2 on same chip modified",
+},
+{
+	.name = "PM_VSU1_SCAL_DOUBLE_ISSUED",
+	.code = 0xb08a,
+	.short_desc = "Double Precision scalar instruction issued on Pipe1",
+	.long_desc = "Double Precision scalar instruction issued on Pipe1",
+},
+{
+	.name = "PM_VSU0_8FLOP",
+	.code = 0xa0a0,
+	.short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+	.long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+},
+{
+	.name = "PM_POWER_EVENT1",
+	.code = 0x1006e,
+	.short_desc = "Power Management Event 1",
+	.long_desc = "Power Management Event 1",
+},
+{
+	.name = "PM_DISP_CLB_HELD_BAL",
+	.code = 0x2092,
+	.short_desc = "Dispatch/CLB Hold: Balance",
+	.long_desc = "Dispatch/CLB Hold: Balance",
+},
+{
+	.name = "PM_VSU1_2FLOP",
+	.code = 0xa09a,
+	.short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+	.long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_LWSYNC_HELD",
+	.code = 0x209a,
+	.short_desc = "LWSYNC held at dispatch",
+	.long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.",
+},
+{
+	.name = "PM_PTEG_FROM_DL2L3_SHR",
+	.code = 0x3c054,
+	.short_desc = "PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.",
+},
+{
+	.name = "PM_INST_FROM_L21_MOD",
+	.code = 0x34046,
+	.short_desc = "Instruction fetched from another L2 on same chip modified",
+	.long_desc = "Instruction fetched from another L2 on same chip modified",
+},
+{
+	.name = "PM_IERAT_XLATE_WR_16MPLUS",
+	.code = 0x40bc,
+	.short_desc = "large page 16M+",
+	.long_desc = "large page 16M+",
+},
+{
+	.name = "PM_IC_REQ_ALL",
+	.code = 0x4888,
+	.short_desc = "Icache requests, prefetch + demand",
+	.long_desc = "Icache requests, prefetch + demand",
+},
+{
+	.name = "PM_DSLB_MISS",
+	.code = 0xd090,
+	.short_desc = "Data SLB Miss - Total of all segment sizes",
+	.long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.",
+},
+{
+	.name = "PM_L3_MISS",
+	.code = 0x1f082,
+	.short_desc = "L3 Misses ",
+	.long_desc = "L3 Misses ",
+},
+{
+	.name = "PM_LSU0_L1_PREF",
+	.code = 0xd0b8,
+	.short_desc = " LS0 L1 cache data prefetches",
+	.long_desc = " LS0 L1 cache data prefetches",
+},
+{
+	.name = "PM_VSU_SCALAR_SINGLE_ISSUED",
+	.code = 0xb884,
+	.short_desc = "Single Precision scalar instruction issued on Pipe0",
+	.long_desc = "Single Precision scalar instruction issued on Pipe0",
+},
+{
+	.name = "PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE",
+	.code = 0xd0be,
+	.short_desc = "LS1  Dcache Strided prefetch stream confirmed",
+	.long_desc = "LS1  Dcache Strided prefetch stream confirmed",
+},
+{
+	.name = "PM_L2_INST",
+	.code = 0x36080,
+	.short_desc = "Instruction Load Count",
+	.long_desc = "Instruction Load Count",
+},
+{
+	.name = "PM_VSU0_FRSP",
+	.code = 0xa0b4,
+	.short_desc = "Round to single precision instruction executed",
+	.long_desc = "Round to single precision instruction executed",
+},
+{
+	.name = "PM_FLUSH_DISP",
+	.code = 0x2082,
+	.short_desc = "Dispatch flush",
+	.long_desc = "Dispatch flush",
+},
+{
+	.name = "PM_PTEG_FROM_L2MISS",
+	.code = 0x4c058,
+	.short_desc = "PTEG loaded from L2 miss",
+	.long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.",
+},
+{
+	.name = "PM_VSU1_DQ_ISSUED",
+	.code = 0xb09a,
+	.short_desc = "128BIT Decimal Issued on Pipe1",
+	.long_desc = "128BIT Decimal Issued on Pipe1",
+},
+{
+	.name = "PM_CMPLU_STALL_LSU",
+	.code = 0x20012,
+	.short_desc = "Completion stall caused by LSU instruction",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DMEM",
+	.code = 0x1d04a,
+	.short_desc = "Marked data loaded from distant memory",
+	.long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.",
+},
+{
+	.name = "PM_LSU_FLUSH_ULD",
+	.code = 0xc8b0,
+	.short_desc = "Flush: Unaligned Load",
+	.long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1).  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_PTEG_FROM_LMEM",
+	.code = 0x4c052,
+	.short_desc = "PTEG loaded from local memory",
+	.long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.",
+},
+{
+	.name = "PM_MRK_DERAT_MISS_16M",
+	.code = 0x3d05c,
+	.short_desc = "Marked DERAT misses for 16M page",
+	.long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_THRD_ALL_RUN_CYC",
+	.code = 0x2000c,
+	.short_desc = "All Threads in run_cycles",
+	.long_desc = "Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.",
+},
+{
+	.name = "PM_MEM0_PREFETCH_DISP",
+	.code = 0x20083,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1",
+},
+{
+	.name = "PM_MRK_STALL_CMPLU_CYC_COUNT",
+	.code = 0x3003f,
+	.short_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
+	.long_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
+},
+{
+	.name = "PM_DATA_FROM_DL2L3_MOD",
+	.code = 0x3c04c,
+	.short_desc = "Data loaded from distant L2 or L3 modified",
+	.long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load",
+},
+{
+	.name = "PM_VSU_FRSP",
+	.code = 0xa8b4,
+	.short_desc = "Round to single precision instruction executed",
+	.long_desc = "Round to single precision instruction executed",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L21_MOD",
+	.code = 0x3d046,
+	.short_desc = "Marked data loaded from another L2 on same chip modified",
+	.long_desc = "Marked data loaded from another L2 on same chip modified",
+},
+{
+	.name = "PM_PMC1_OVERFLOW",
+	.code = 0x20010,
+	.short_desc = "Overflow from counter 1",
+	.long_desc = "Overflows from PMC1 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_VSU0_SINGLE",
+	.code = 0xa0a8,
+	.short_desc = "FPU single precision",
+	.long_desc = "VSU0 executed single precision instruction",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L3MISS",
+	.code = 0x2d058,
+	.short_desc = "Marked PTEG loaded from L3 miss",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L31_SHR",
+	.code = 0x2d056,
+	.short_desc = "Marked PTEG loaded from another L3 on same chip shared",
+	.long_desc = "Marked PTEG loaded from another L3 on same chip shared",
+},
+{
+	.name = "PM_VSU0_VECTOR_SP_ISSUED",
+	.code = 0xb090,
+	.short_desc = "Single Precision vector instruction issued (executed)",
+	.long_desc = "Single Precision vector instruction issued (executed)",
+},
+{
+	.name = "PM_VSU1_FEST",
+	.code = 0xa0ba,
+	.short_desc = "Estimate instruction executed",
+	.long_desc = "Estimate instruction executed",
+},
+{
+	.name = "PM_MRK_INST_DISP",
+	.code = 0x20030,
+	.short_desc = "marked instruction dispatch",
+	.long_desc = "A marked instruction was dispatched",
+},
+{
+	.name = "PM_VSU0_COMPLEX_ISSUED",
+	.code = 0xb096,
+	.short_desc = "Complex VMX instruction issued",
+	.long_desc = "Complex VMX instruction issued",
+},
+{
+	.name = "PM_LSU1_FLUSH_UST",
+	.code = 0xc0b6,
+	.short_desc = "LS1 Flush: Unaligned Store",
+	.long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)",
+},
+{
+	.name = "PM_INST_CMPL",
+	.code = 0x2,
+	.short_desc = "# PPC Instructions Finished",
+	.long_desc = "Number of PowerPC Instructions that completed.",
+},
+{
+	.name = "PM_FXU_IDLE",
+	.code = 0x1000e,
+	.short_desc = "fxu0 idle and fxu1 idle",
+	.long_desc = "FXU0 and FXU1 are both idle.",
+},
+{
+	.name = "PM_LSU0_FLUSH_ULD",
+	.code = 0xc0b0,
+	.short_desc = "LS0 Flush: Unaligned Load",
+	.long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DL2L3_MOD",
+	.code = 0x3d04c,
+	.short_desc = "Marked data loaded from distant L2 or L3 modified",
+	.long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a marked load.",
+},
+{
+	.name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC",
+	.code = 0x3001c,
+	.short_desc = "ALL threads lsu empty (lmq and srq empty)",
+	.long_desc = "ALL threads lsu empty (lmq and srq empty)",
+},
+{
+	.name = "PM_LSU1_REJECT_LMQ_FULL",
+	.code = 0xc0a6,
+	.short_desc = "LS1 Reject: LMQ Full (LHR)",
+	.long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all eight entries are full, subsequent load instructions are rejected.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L21_MOD",
+	.code = 0x3e056,
+	.short_desc = "Instruction PTEG loaded from another L2 on same chip modified",
+	.long_desc = "Instruction PTEG loaded from another L2 on same chip modified",
+},
+{
+	.name = "PM_INST_FROM_RL2L3_MOD",
+	.code = 0x14042,
+	.short_desc = "Instruction fetched from remote L2 or L3 modified",
+	.long_desc = "An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_SHL_CREATED",
+	.code = 0x5082,
+	.short_desc = "SHL table entry Created",
+	.long_desc = "SHL table entry Created",
+},
+{
+	.name = "PM_L2_ST_HIT",
+	.code = 0x46182,
+	.short_desc = "All successful store dispatches that were L2Hits",
+	.long_desc = "A store request hit in the L2 directory.  This event includes all requests to this L2 from all sources. Total for all slices.",
+},
+{
+	.name = "PM_DATA_FROM_DMEM",
+	.code = 0x1c04a,
+	.short_desc = "Data loaded from distant memory",
+	.long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load",
+},
+{
+	.name = "PM_L3_LD_MISS",
+	.code = 0x2f082,
+	.short_desc = "L3 demand LD Miss",
+	.long_desc = "L3 demand LD Miss",
+},
+{
+	.name = "PM_FXU1_BUSY_FXU0_IDLE",
+	.code = 0x4000e,
+	.short_desc = "fxu0 idle and fxu1 busy. ",
+	.long_desc = "FXU0 was idle while FXU1 was busy",
+},
+{
+	.name = "PM_DISP_CLB_HELD_RES",
+	.code = 0x2094,
+	.short_desc = "Dispatch/CLB Hold: Resource",
+	.long_desc = "Dispatch/CLB Hold: Resource",
+},
+{
+	.name = "PM_L2_SN_SX_I_DONE",
+	.code = 0x36382,
+	.short_desc = "SNP dispatched and went from Sx or Tx to Ix",
+	.long_desc = "SNP dispatched and went from Sx or Tx to Ix",
+},
+{
+	.name = "PM_GRP_CMPL",
+	.code = 0x30004,
+	.short_desc = "group completed",
+	.long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
+},
+{
+	.name = "PM_STCX_CMPL",
+	.code = 0xc098,
+	.short_desc = "STCX executed",
+	.long_desc = "Conditional stores with reservation completed",
+},
+{
+	.name = "PM_VSU0_2FLOP",
+	.code = 0xa098,
+	.short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+	.long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_L3_PREF_MISS",
+	.code = 0x3f082,
+	.short_desc = "L3 Prefetch  Directory Miss",
+	.long_desc = "L3 Prefetch  Directory Miss",
+},
+{
+	.name = "PM_LSU_SRQ_SYNC_CYC",
+	.code = 0xd096,
+	.short_desc = "A sync is in the SRQ",
+	.long_desc = "Cycles that a sync instruction is active in the Store Request Queue.",
+},
+{
+	.name = "PM_LSU_REJECT_ERAT_MISS",
+	.code = 0x20064,
+	.short_desc = "LSU Reject due to ERAT (up to 2 per cycles)",
+	.long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
+},
+{
+	.name = "PM_L1_ICACHE_MISS",
+	.code = 0x200fc,
+	.short_desc = "Demand iCache Miss",
+	.long_desc = "An instruction fetch request missed the L1 cache.",
+},
+{
+	.name = "PM_LSU1_FLUSH_SRQ",
+	.code = 0xc0be,
+	.short_desc = "LS1 Flush: SRQ",
+	.long_desc = "Load Hit Store flush.  A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions. ",
+},
+{
+	.name = "PM_LD_REF_L1_LSU0",
+	.code = 0xc080,
+	.short_desc = "LS0 L1 D cache load references counted at finish",
+	.long_desc = "Load references to Level 1 Data Cache, by unit 0.",
+},
+{
+	.name = "PM_VSU0_FEST",
+	.code = 0xa0b8,
+	.short_desc = "Estimate instruction executed",
+	.long_desc = "Estimate instruction executed",
+},
+{
+	.name = "PM_VSU_VECTOR_SINGLE_ISSUED",
+	.code = 0xb890,
+	.short_desc = "Single Precision vector instruction issued (executed)",
+	.long_desc = "Single Precision vector instruction issued (executed)",
+},
+{
+	.name = "PM_FREQ_UP",
+	.code = 0x4000c,
+	.short_desc = "Power Management: Above Threshold A",
+	.long_desc = "Processor frequency was sped up due to power management",
+},
+{
+	.name = "PM_DATA_FROM_LMEM",
+	.code = 0x3c04a,
+	.short_desc = "Data loaded from local memory",
+	.long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.",
+},
+{
+	.name = "PM_LSU1_LDX",
+	.code = 0xc08a,
+	.short_desc = "LS1  Vector Loads",
+	.long_desc = "LS1  Vector Loads",
+},
+{
+	.name = "PM_PMC3_OVERFLOW",
+	.code = 0x40010,
+	.short_desc = "Overflow from counter 3",
+	.long_desc = "Overflows from PMC3 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_MRK_BR_MPRED",
+	.code = 0x30036,
+	.short_desc = "Marked Branch Mispredicted",
+	.long_desc = "A marked branch was mispredicted",
+},
+{
+	.name = "PM_SHL_MATCH",
+	.code = 0x5086,
+	.short_desc = "SHL Table Match",
+	.long_desc = "SHL Table Match",
+},
+{
+	.name = "PM_MRK_BR_TAKEN",
+	.code = 0x10036,
+	.short_desc = "Marked Branch Taken",
+	.long_desc = "A marked branch was taken",
+},
+{
+	.name = "PM_CMPLU_STALL_BRU",
+	.code = 0x4004e,
+	.short_desc = "Completion stall due to BRU",
+	.long_desc = "Completion stall due to BRU",
+},
+{
+	.name = "PM_ISLB_MISS",
+	.code = 0xd092,
+	.short_desc = "Instruction SLB Miss - Tota of all segment sizes",
+	.long_desc = "A SLB miss for an instruction fetch as occurred",
+},
+{
+	.name = "PM_CYC",
+	.code = 0x1e,
+	.short_desc = "Cycles",
+	.long_desc = "Processor Cycles",
+},
+{
+	.name = "PM_DISP_HELD_THERMAL",
+	.code = 0x30006,
+	.short_desc = "Dispatch Held due to Thermal",
+	.long_desc = "Dispatch Held due to Thermal",
+},
+{
+	.name = "PM_INST_PTEG_FROM_RL2L3_SHR",
+	.code = 0x2e054,
+	.short_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+},
+{
+	.name = "PM_LSU1_SRQ_STFWD",
+	.code = 0xc0a2,
+	.short_desc = "LS1 SRQ forwarded data to a load",
+	.long_desc = "Data from a store instruction was forwarded to a load on unit 1.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+},
+{
+	.name = "PM_GCT_NOSLOT_BR_MPRED",
+	.code = 0x4001a,
+	.short_desc = "GCT empty by branch  mispredict",
+	.long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.",
+},
+{
+	.name = "PM_1PLUS_PPC_CMPL",
+	.code = 0x100f2,
+	.short_desc = "1 or more ppc  insts finished",
+	.long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
+},
+{
+	.name = "PM_PTEG_FROM_DMEM",
+	.code = 0x2c052,
+	.short_desc = "PTEG loaded from distant memory",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.",
+},
+{
+	.name = "PM_VSU_2FLOP",
+	.code = 0xa898,
+	.short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+	.long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_GCT_FULL_CYC",
+	.code = 0x4086,
+	.short_desc = "Cycles No room in EAT",
+	.long_desc = "The Global Completion Table is completely full.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L3_CYC",
+	.code = 0x40020,
+	.short_desc = "Marked ld latency Data source 0001 (L3)",
+	.long_desc = "Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+	.name = "PM_LSU_SRQ_S0_ALLOC",
+	.code = 0xd09d,
+	.short_desc = "Slot 0 of SRQ valid",
+	.long_desc = "Slot 0 of SRQ valid",
+},
+{
+	.name = "PM_MRK_DERAT_MISS_4K",
+	.code = 0x1d05c,
+	.short_desc = "Marked DERAT misses for 4K page",
+	.long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_BR_MPRED_TA",
+	.code = 0x40ae,
+	.short_desc = "Branch mispredict - target address",
+	.long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L2MISS",
+	.code = 0x4e058,
+	.short_desc = "Instruction PTEG loaded from L2 miss",
+	.long_desc = "Instruction PTEG loaded from L2 miss",
+},
+{
+	.name = "PM_DPU_HELD_POWER",
+	.code = 0x20006,
+	.short_desc = "Dispatch Held due to Power Management",
+	.long_desc = "Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time",
+},
+{
+	.name = "PM_RUN_INST_CMPL",
+	.code = 0x400fa,
+	.short_desc = "Run_Instructions",
+	.long_desc = "Number of run instructions completed. ",
+},
+{
+	.name = "PM_MRK_VSU_FIN",
+	.code = 0x30032,
+	.short_desc = "vsu (fpu) marked  instr finish",
+	.long_desc = "vsu (fpu) marked  instr finish",
+},
+{
+	.name = "PM_LSU_SRQ_S0_VALID",
+	.code = 0xd09c,
+	.short_desc = "Slot 0 of SRQ valid",
+	.long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the SRQ is split between the two threads (16 entries each).",
+},
+{
+	.name = "PM_GCT_EMPTY_CYC",
+	.code = 0x20008,
+	.short_desc = "GCT empty, all threads",
+	.long_desc = "Cycles when the Global Completion Table was completely empty.  No thread had an entry allocated.",
+},
+{
+	.name = "PM_IOPS_DISP",
+	.code = 0x30014,
+	.short_desc = "IOPS dispatched",
+	.long_desc = "IOPS dispatched",
+},
+{
+	.name = "PM_RUN_SPURR",
+	.code = 0x10008,
+	.short_desc = "Run SPURR",
+	.long_desc = "Run SPURR",
+},
+{
+	.name = "PM_PTEG_FROM_L21_MOD",
+	.code = 0x3c056,
+	.short_desc = "PTEG loaded from another L2 on same chip modified",
+	.long_desc = "PTEG loaded from another L2 on same chip modified",
+},
+{
+	.name = "PM_VSU0_1FLOP",
+	.code = 0xa080,
+	.short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+	.long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+},
+{
+	.name = "PM_SNOOP_TLBIE",
+	.code = 0xd0b2,
+	.short_desc = "TLBIE snoop",
+	.long_desc = "A tlbie was snooped from another processor.",
+},
+{
+	.name = "PM_DATA_FROM_L3MISS",
+	.code = 0x2c048,
+	.short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
+	.long_desc = "The processor's Data Cache was reloaded from beyond L3 due to a demand load",
+},
+{
+	.name = "PM_VSU_SINGLE",
+	.code = 0xa8a8,
+	.short_desc = "Vector or Scalar single precision",
+	.long_desc = "Vector or Scalar single precision",
+},
+{
+	.name = "PM_DTLB_MISS_16G",
+	.code = 0x1c05e,
+	.short_desc = "Data TLB miss for 16G page",
+	.long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_CMPLU_STALL_VECTOR",
+	.code = 0x2001c,
+	.short_desc = "Completion stall caused by Vector instruction",
+	.long_desc = "Completion stall caused by Vector instruction",
+},
+{
+	.name = "PM_FLUSH",
+	.code = 0x400f8,
+	.short_desc = "Flush (any type)",
+	.long_desc = "Flushes occurred including LSU and Branch flushes.",
+},
+{
+	.name = "PM_L2_LD_HIT",
+	.code = 0x36182,
+	.short_desc = "All successful load dispatches that were L2 hits",
+	.long_desc = "A load request (data or instruction) hit in the L2 directory.  Includes speculative, prefetched, and demand requests.  This event includes all requests to this L2 from all sources.  Total for all slices",
+},
+{
+	.name = "PM_NEST_PAIR2_AND",
+	.code = 0x30883,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND",
+},
+{
+	.name = "PM_VSU1_1FLOP",
+	.code = 0xa082,
+	.short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+	.long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+},
+{
+	.name = "PM_IC_PREF_REQ",
+	.code = 0x408a,
+	.short_desc = "Instruction prefetch requests",
+	.long_desc = "An instruction prefetch request has been made.",
+},
+{
+	.name = "PM_L3_LD_HIT",
+	.code = 0x2f080,
+	.short_desc = "L3 demand LD Hits",
+	.long_desc = "L3 demand LD Hits",
+},
+{
+	.name = "PM_GCT_NOSLOT_IC_MISS",
+	.code = 0x2001a,
+	.short_desc = "GCT empty by I cache miss",
+	.long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.",
+},
+{
+	.name = "PM_DISP_HELD",
+	.code = 0x10006,
+	.short_desc = "Dispatch Held",
+	.long_desc = "Dispatch Held",
+},
+{
+	.name = "PM_L2_LD",
+	.code = 0x16080,
+	.short_desc = "Data Load Count",
+	.long_desc = "Data Load Count",
+},
+{
+	.name = "PM_LSU_FLUSH_SRQ",
+	.code = 0xc8bc,
+	.short_desc = "Flush: SRQ",
+	.long_desc = "Load Hit Store flush.  A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_BC_PLUS_8_CONV",
+	.code = 0x40b8,
+	.short_desc = "BC+8 Converted",
+	.long_desc = "BC+8 Converted",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L31_MOD_CYC",
+	.code = 0x40026,
+	.short_desc = "Marked ld latency Data source 0111  (L3.1 M same chip)",
+	.long_desc = "Marked ld latency Data source 0111  (L3.1 M same chip)",
+},
+{
+	.name = "PM_CMPLU_STALL_VECTOR_LONG",
+	.code = 0x4004a,
+	.short_desc = "completion stall due to long latency vector instruction",
+	.long_desc = "completion stall due to long latency vector instruction",
+},
+{
+	.name = "PM_L2_RCST_BUSY_RC_FULL",
+	.code = 0x26282,
+	.short_desc = " L2  activated Busy to the core for stores due to all RC full",
+	.long_desc = " L2  activated Busy to the core for stores due to all RC full",
+},
+{
+	.name = "PM_TB_BIT_TRANS",
+	.code = 0x300f8,
+	.short_desc = "Time Base bit transition",
+	.long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
+},
+{
+	.name = "PM_THERMAL_MAX",
+	.code = 0x40006,
+	.short_desc = "Processor In Thermal MAX",
+	.long_desc = "The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.",
+},
+{
+	.name = "PM_LSU1_FLUSH_ULD",
+	.code = 0xc0b2,
+	.short_desc = "LS 1 Flush: Unaligned Load",
+	.long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).",
+},
+{
+	.name = "PM_LSU1_REJECT_LHS",
+	.code = 0xc0ae,
+	.short_desc = "LS1  Reject: Load Hit Store",
+	.long_desc = "Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.",
+},
+{
+	.name = "PM_LSU_LRQ_S0_ALLOC",
+	.code = 0xd09f,
+	.short_desc = "Slot 0 of LRQ valid",
+	.long_desc = "Slot 0 of LRQ valid",
+},
+{
+	.name = "PM_L3_CO_L31",
+	.code = 0x4f080,
+	.short_desc = "L3 Castouts to Memory",
+	.long_desc = "L3 Castouts to Memory",
+},
+{
+	.name = "PM_POWER_EVENT4",
+	.code = 0x4006e,
+	.short_desc = "Power Management Event 4",
+	.long_desc = "Power Management Event 4",
+},
+{
+	.name = "PM_DATA_FROM_L31_SHR",
+	.code = 0x1c04e,
+	.short_desc = "Data loaded from another L3 on same chip shared",
+	.long_desc = "Data loaded from another L3 on same chip shared",
+},
+{
+	.name = "PM_BR_UNCOND",
+	.code = 0x409e,
+	.short_desc = "Unconditional Branch",
+	.long_desc = "An unconditional branch was executed.",
+},
+{
+	.name = "PM_LSU1_DC_PREF_STREAM_ALLOC",
+	.code = 0xd0aa,
+	.short_desc = "LS 1 D cache new prefetch stream allocated",
+	.long_desc = "LS 1 D cache new prefetch stream allocated",
+},
+{
+	.name = "PM_PMC4_REWIND",
+	.code = 0x10020,
+	.short_desc = "PMC4 Rewind Event",
+	.long_desc = "PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.",
+},
+{
+	.name = "PM_L2_RCLD_DISP",
+	.code = 0x16280,
+	.short_desc = " L2  RC load dispatch attempt",
+	.long_desc = " L2  RC load dispatch attempt",
+},
+{
+	.name = "PM_THRD_PRIO_2_3_CYC",
+	.code = 0x40b2,
+	.short_desc = " Cycles thread running at priority level 2 or 3",
+	.long_desc = " Cycles thread running at priority level 2 or 3",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L2MISS",
+	.code = 0x4d058,
+	.short_desc = "Marked PTEG loaded from L2 miss",
+	.long_desc = "A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.",
+},
+{
+	.name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+	.code = 0x4098,
+	.short_desc = " L2 I cache demand request due to BHT redirect",
+	.long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).",
+},
+{
+	.name = "PM_LSU_DERAT_MISS",
+	.code = 0x200f6,
+	.short_desc = "DERAT Reloaded due to a DERAT miss",
+	.long_desc = "Total D-ERAT Misses.  Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_IC_PREF_CANCEL_L2",
+	.code = 0x4094,
+	.short_desc = "L2 Squashed request",
+	.long_desc = "L2 Squashed request",
+},
+{
+	.name = "PM_MRK_FIN_STALL_CYC_COUNT",
+	.code = 0x1003d,
+	.short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
+	.long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
+},
+{
+	.name = "PM_BR_PRED_CCACHE",
+	.code = 0x40a0,
+	.short_desc = "Count Cache Predictions",
+	.long_desc = "The count value of a Branch and Count instruction was predicted",
+},
+{
+	.name = "PM_GCT_UTIL_1_TO_2_SLOTS",
+	.code = 0x209c,
+	.short_desc = "GCT Utilization 1-2 entries",
+	.long_desc = "GCT Utilization 1-2 entries",
+},
+{
+	.name = "PM_MRK_ST_CMPL_INT",
+	.code = 0x30034,
+	.short_desc = "marked  store complete (data home) with intervention",
+	.long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
+},
+{
+	.name = "PM_LSU_TWO_TABLEWALK_CYC",
+	.code = 0xd0a6,
+	.short_desc = "Cycles when two tablewalks pending on this thread",
+	.long_desc = "Cycles when two tablewalks pending on this thread",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L3MISS",
+	.code = 0x2d048,
+	.short_desc = "Marked data loaded from L3 miss",
+	.long_desc = "DL1 was reloaded from beyond L3 due to a marked load.",
+},
+{
+	.name = "PM_GCT_NOSLOT_CYC",
+	.code = 0x100f8,
+	.short_desc = "No itags assigned ",
+	.long_desc = "Cycles when the Global Completion Table has no slots from this thread.",
+},
+{
+	.name = "PM_LSU_SET_MPRED",
+	.code = 0xc0a8,
+	.short_desc = "Line already in cache at reload time",
+	.long_desc = "Line already in cache at reload time",
+},
+{
+	.name = "PM_FLUSH_DISP_TLBIE",
+	.code = 0x208a,
+	.short_desc = "Dispatch Flush: TLBIE",
+	.long_desc = "Dispatch Flush: TLBIE",
+},
+{
+	.name = "PM_VSU1_FCONV",
+	.code = 0xa0b2,
+	.short_desc = "Convert instruction executed",
+	.long_desc = "Convert instruction executed",
+},
+{
+	.name = "PM_DERAT_MISS_16G",
+	.code = 0x4c05c,
+	.short_desc = "DERAT misses for 16G page",
+	.long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_INST_FROM_LMEM",
+	.code = 0x3404a,
+	.short_desc = "Instruction fetched from local memory",
+	.long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+	.code = 0x409a,
+	.short_desc = " L2 I cache demand request due to branch redirect",
+	.long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).",
+},
+{
+	.name = "PM_CMPLU_STALL_SCALAR_LONG",
+	.code = 0x20018,
+	.short_desc = "Completion stall caused by long latency scalar instruction",
+	.long_desc = "Completion stall caused by long latency scalar instruction",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L2",
+	.code = 0x1e050,
+	.short_desc = "Instruction PTEG loaded from L2",
+	.long_desc = "Instruction PTEG loaded from L2",
+},
+{
+	.name = "PM_PTEG_FROM_L2",
+	.code = 0x1c050,
+	.short_desc = "PTEG loaded from L2",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L21_SHR_CYC",
+	.code = 0x20024,
+	.short_desc = "Marked ld latency Data source 0100 (L2.1 S)",
+	.long_desc = "Marked load latency Data source 0100 (L2.1 S)",
+},
+{
+	.name = "PM_MRK_DTLB_MISS_4K",
+	.code = 0x2d05a,
+	.short_desc = "Marked Data TLB misses for 4K page",
+	.long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_VSU0_FPSCR",
+	.code = 0xb09c,
+	.short_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
+	.long_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
+},
+{
+	.name = "PM_VSU1_VECT_DOUBLE_ISSUED",
+	.code = 0xb082,
+	.short_desc = "Double Precision vector instruction issued on Pipe1",
+	.long_desc = "Double Precision vector instruction issued on Pipe1",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_RL2L3_MOD",
+	.code = 0x1d052,
+	.short_desc = "Marked PTEG loaded from remote L2 or L3 modified",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.",
+},
+{
+	.name = "PM_MEM0_RQ_DISP",
+	.code = 0x10083,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1",
+},
+{
+	.name = "PM_L2_LD_MISS",
+	.code = 0x26080,
+	.short_desc = "Data Load Miss",
+	.long_desc = "Data Load Miss",
+},
+{
+	.name = "PM_VMX_RESULT_SAT_1",
+	.code = 0xb0a0,
+	.short_desc = "Valid result with sat=1",
+	.long_desc = "Valid result with sat=1",
+},
+{
+	.name = "PM_L1_PREF",
+	.code = 0xd8b8,
+	.short_desc = "L1 Prefetches",
+	.long_desc = "A request to prefetch data into the L1 was made",
+},
+{
+	.name = "PM_MRK_DATA_FROM_LMEM_CYC",
+	.code = 0x2002c,
+	.short_desc = "Marked ld latency Data Source 1100 (Local Memory)",
+	.long_desc = "Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+	.name = "PM_GRP_IC_MISS_NONSPEC",
+	.code = 0x1000c,
+	.short_desc = "Group experienced non-speculative I cache miss",
+	.long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.",
+},
+{
+	.name = "PM_PB_NODE_PUMP",
+	.code = 0x10081,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0",
+},
+{
+	.name = "PM_SHL_MERGED",
+	.code = 0x5084,
+	.short_desc = "SHL table entry merged with existing",
+	.long_desc = "SHL table entry merged with existing",
+},
+{
+	.name = "PM_NEST_PAIR1_ADD",
+	.code = 0x20881,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD",
+},
+{
+	.name = "PM_DATA_FROM_L3",
+	.code = 0x1c048,
+	.short_desc = "Data loaded from L3",
+	.long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.",
+},
+{
+	.name = "PM_LSU_FLUSH",
+	.code = 0x208e,
+	.short_desc = "Flush initiated by LSU",
+	.long_desc = "A flush was initiated by the Load Store Unit.",
+},
+{
+	.name = "PM_LSU_SRQ_SYNC_COUNT",
+	.code = 0xd097,
+	.short_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
+	.long_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
+},
+{
+	.name = "PM_PMC2_OVERFLOW",
+	.code = 0x30010,
+	.short_desc = "Overflow from counter 2",
+	.long_desc = "Overflows from PMC2 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_LSU_LDF",
+	.code = 0xc884,
+	.short_desc = "All Scalar Loads",
+	.long_desc = "LSU executed Floating Point load instruction.  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_POWER_EVENT3",
+	.code = 0x3006e,
+	.short_desc = "Power Management Event 3",
+	.long_desc = "Power Management Event 3",
+},
+{
+	.name = "PM_DISP_WT",
+	.code = 0x30008,
+	.short_desc = "Dispatched Starved (not held, nothing to dispatch)",
+	.long_desc = "Dispatched Starved (not held, nothing to dispatch)",
+},
+{
+	.name = "PM_CMPLU_STALL_REJECT",
+	.code = 0x40016,
+	.short_desc = "Completion stall caused by reject",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.",
+},
+{
+	.name = "PM_IC_BANK_CONFLICT",
+	.code = 0x4082,
+	.short_desc = "Read blocked due to interleave conflict.  ",
+	.long_desc = "Read blocked due to interleave conflict.  ",
+},
+{
+	.name = "PM_BR_MPRED_CR_TA",
+	.code = 0x48ae,
+	.short_desc = "Branch mispredict - taken/not taken and target",
+	.long_desc = "Branch mispredict - taken/not taken and target",
+},
+{
+	.name = "PM_L2_INST_MISS",
+	.code = 0x36082,
+	.short_desc = "Instruction Load Misses",
+	.long_desc = "Instruction Load Misses",
+},
+{
+	.name = "PM_CMPLU_STALL_ERAT_MISS",
+	.code = 0x40018,
+	.short_desc = "Completion stall caused by ERAT miss",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of  PM_CMPLU_STALL_REJECT.",
+},
+{
+	.name = "PM_NEST_PAIR2_ADD",
+	.code = 0x30881,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD",
+},
+{
+	.name = "PM_MRK_LSU_FLUSH",
+	.code = 0xd08c,
+	.short_desc = "Flush: (marked) : All Cases",
+	.long_desc = "Marked flush initiated by LSU",
+},
+{
+	.name = "PM_L2_LDST",
+	.code = 0x16880,
+	.short_desc = "Data Load+Store Count",
+	.long_desc = "Data Load+Store Count",
+},
+{
+	.name = "PM_INST_FROM_L31_SHR",
+	.code = 0x1404e,
+	.short_desc = "Instruction fetched from another L3 on same chip shared",
+	.long_desc = "Instruction fetched from another L3 on same chip shared",
+},
+{
+	.name = "PM_VSU0_FIN",
+	.code = 0xa0bc,
+	.short_desc = "VSU0 Finished an instruction",
+	.long_desc = "VSU0 Finished an instruction",
+},
+{
+	.name = "PM_LARX_LSU",
+	.code = 0xc894,
+	.short_desc = "Larx Finished",
+	.long_desc = "Larx Finished",
+},
+{
+	.name = "PM_INST_FROM_RMEM",
+	.code = 0x34042,
+	.short_desc = "Instruction fetched from remote memory",
+	.long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on.  Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_DISP_CLB_HELD_TLBIE",
+	.code = 0x2096,
+	.short_desc = "Dispatch Hold: Due to TLBIE",
+	.long_desc = "Dispatch Hold: Due to TLBIE",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DMEM_CYC",
+	.code = 0x2002e,
+	.short_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
+	.long_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
+},
+{
+	.name = "PM_BR_PRED_CR",
+	.code = 0x40a8,
+	.short_desc = "Branch predict - taken/not taken",
+	.long_desc = "A conditional branch instruction was predicted as taken or not taken.",
+},
+{
+	.name = "PM_LSU_REJECT",
+	.code = 0x10064,
+	.short_desc = "LSU Reject (up to 2 per cycle)",
+	.long_desc = "The Load Store Unit rejected an instruction. Combined Unit 0 + 1",
+},
+{
+	.name = "PM_GCT_UTIL_3_TO_6_SLOTS",
+	.code = 0x209e,
+	.short_desc = "GCT Utilization 3-6 entries",
+	.long_desc = "GCT Utilization 3-6 entries",
+},
+{
+	.name = "PM_CMPLU_STALL_END_GCT_NOSLOT",
+	.code = 0x10028,
+	.short_desc = "Count ended because GCT went empty",
+	.long_desc = "Count ended because GCT went empty",
+},
+{
+	.name = "PM_LSU0_REJECT_LMQ_FULL",
+	.code = 0xc0a4,
+	.short_desc = "LS0 Reject: LMQ Full (LHR)",
+	.long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all eight entries are full, subsequent load instructions are rejected.",
+},
+{
+	.name = "PM_VSU_FEST",
+	.code = 0xa8b8,
+	.short_desc = "Estimate instruction executed",
+	.long_desc = "Estimate instruction executed",
+},
+{
+	.name = "PM_NEST_PAIR0_AND",
+	.code = 0x10883,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND",
+},
+{
+	.name = "PM_PTEG_FROM_L3",
+	.code = 0x2c050,
+	.short_desc = "PTEG loaded from L3",
+	.long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.",
+},
+{
+	.name = "PM_POWER_EVENT2",
+	.code = 0x2006e,
+	.short_desc = "Power Management Event 2",
+	.long_desc = "Power Management Event 2",
+},
+{
+	.name = "PM_IC_PREF_CANCEL_PAGE",
+	.code = 0x4090,
+	.short_desc = "Prefetch Canceled due to page boundary",
+	.long_desc = "Prefetch Canceled due to page boundary",
+},
+{
+	.name = "PM_VSU0_FSQRT_FDIV",
+	.code = 0xa088,
+	.short_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+	.long_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+},
+{
+	.name = "PM_MRK_GRP_CMPL",
+	.code = 0x40030,
+	.short_desc = "Marked group complete",
+	.long_desc = "A group containing a sampled instruction completed.  Microcoded instructions that span multiple groups will generate this event once per group.",
+},
+{
+	.name = "PM_VSU0_SCAL_DOUBLE_ISSUED",
+	.code = 0xb088,
+	.short_desc = "Double Precision scalar instruction issued on Pipe0",
+	.long_desc = "Double Precision scalar instruction issued on Pipe0",
+},
+{
+	.name = "PM_GRP_DISP",
+	.code = 0x3000a,
+	.short_desc = "dispatch_success (Group Dispatched)",
+	.long_desc = "A group was dispatched",
+},
+{
+	.name = "PM_LSU0_LDX",
+	.code = 0xc088,
+	.short_desc = "LS0 Vector Loads",
+	.long_desc = "LS0 Vector Loads",
+},
+{
+	.name = "PM_DATA_FROM_L2",
+	.code = 0x1c040,
+	.short_desc = "Data loaded from L2",
+	.long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RL2L3_MOD",
+	.code = 0x1d042,
+	.short_desc = "Marked data loaded from remote L2 or L3 modified",
+	.long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a marked load.",
+},
+{
+	.name = "PM_LD_REF_L1",
+	.code = 0xc880,
+	.short_desc = " L1 D cache load references counted at finish",
+	.long_desc = " L1 D cache load references counted at finish",
+},
+{
+	.name = "PM_VSU0_VECT_DOUBLE_ISSUED",
+	.code = 0xb080,
+	.short_desc = "Double Precision vector instruction issued on Pipe0",
+	.long_desc = "Double Precision vector instruction issued on Pipe0",
+},
+{
+	.name = "PM_VSU1_2FLOP_DOUBLE",
+	.code = 0xa08e,
+	.short_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)  ",
+	.long_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)  ",
+},
+{
+	.name = "PM_THRD_PRIO_6_7_CYC",
+	.code = 0x40b6,
+	.short_desc = " Cycles thread running at priority level 6 or 7",
+	.long_desc = " Cycles thread running at priority level 6 or 7",
+},
+{
+	.name = "PM_BC_PLUS_8_RSLV_TAKEN",
+	.code = 0x40ba,
+	.short_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled",
+	.long_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled",
+},
+{
+	.name = "PM_BR_MPRED_CR",
+	.code = 0x40ac,
+	.short_desc = "Branch mispredict - taken/not taken",
+	.long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken.  The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
+},
+{
+	.name = "PM_L3_CO_MEM",
+	.code = 0x4f082,
+	.short_desc = "L3 Castouts to L3.1",
+	.long_desc = "L3 Castouts to L3.1",
+},
+{
+	.name = "PM_LD_MISS_L1",
+	.code = 0x400f0,
+	.short_desc = "Load Missed L1",
+	.long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.",
+},
+{
+	.name = "PM_DATA_FROM_RL2L3_MOD",
+	.code = 0x1c042,
+	.short_desc = "Data loaded from remote L2 or L3 modified",
+	.long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load",
+},
+{
+	.name = "PM_LSU_SRQ_FULL_CYC",
+	.code = 0x1001a,
+	.short_desc = "Storage Queue is full and is blocking dispatch",
+	.long_desc = "Cycles the Store Request Queue is full.",
+},
+{
+	.name = "PM_TABLEWALK_CYC",
+	.code = 0x10026,
+	.short_desc = "Cycles when a tablewalk (I or D) is active",
+	.long_desc = "Cycles doing instruction or data tablewalks",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_RMEM",
+	.code = 0x3d052,
+	.short_desc = "Marked PTEG loaded from remote memory",
+	.long_desc = "A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB",
+},
+{
+	.name = "PM_LSU_SRQ_STFWD",
+	.code = 0xc8a0,
+	.short_desc = "Load got data from a store",
+	.long_desc = "Data from a store instruction was forwarded to a load.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_RMEM",
+	.code = 0x3e052,
+	.short_desc = "Instruction PTEG loaded from remote memory",
+	.long_desc = "Instruction PTEG loaded from remote memory",
+},
+{
+	.name = "PM_FXU0_FIN",
+	.code = 0x10004,
+	.short_desc = "FXU0 Finished",
+	.long_desc = "The Fixed Point unit 0 finished an instruction and produced a result.  Instructions that finish may not necessary complete.",
+},
+{
+	.name = "PM_LSU1_L1_SW_PREF",
+	.code = 0xc09e,
+	.short_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches",
+	.long_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches",
+},
+{
+	.name = "PM_PTEG_FROM_L31_MOD",
+	.code = 0x1c054,
+	.short_desc = "PTEG loaded from another L3 on same chip modified",
+	.long_desc = "PTEG loaded from another L3 on same chip modified",
+},
+{
+	.name = "PM_PMC5_OVERFLOW",
+	.code = 0x10024,
+	.short_desc = "Overflow from counter 5",
+	.long_desc = "Overflows from PMC5 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_LD_REF_L1_LSU1",
+	.code = 0xc082,
+	.short_desc = "LS1 L1 D cache load references counted at finish",
+	.long_desc = "Load references to Level 1 Data Cache, by unit 1.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L21_SHR",
+	.code = 0x4e056,
+	.short_desc = "Instruction PTEG loaded from another L2 on same chip shared",
+	.long_desc = "Instruction PTEG loaded from another L2 on same chip shared",
+},
+{
+	.name = "PM_CMPLU_STALL_THRD",
+	.code = 0x1001c,
+	.short_desc = "Completion Stalled due to thread conflict.  Group ready to complete but it was another thread's turn",
+	.long_desc = "Completion Stalled due to thread conflict.  Group ready to complete but it was another thread's turn",
+},
+{
+	.name = "PM_DATA_FROM_RMEM",
+	.code = 0x3c042,
+	.short_desc = "Data loaded from remote memory",
+	.long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.",
+},
+{
+	.name = "PM_VSU0_SCAL_SINGLE_ISSUED",
+	.code = 0xb084,
+	.short_desc = "Single Precision scalar instruction issued on Pipe0",
+	.long_desc = "Single Precision scalar instruction issued on Pipe0",
+},
+{
+	.name = "PM_BR_MPRED_LSTACK",
+	.code = 0x40a6,
+	.short_desc = "Branch Mispredict due to Link Stack",
+	.long_desc = "Branch Mispredict due to Link Stack",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
+	.code = 0x40028,
+	.short_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
+	.long_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
+},
+{
+	.name = "PM_LSU0_FLUSH_UST",
+	.code = 0xc0b4,
+	.short_desc = "LS0 Flush: Unaligned Store",
+	.long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).",
+},
+{
+	.name = "PM_LSU_NCST",
+	.code = 0xc090,
+	.short_desc = "Non-cachable Stores sent to nest",
+	.long_desc = "Non-cachable Stores sent to nest",
+},
+{
+	.name = "PM_BR_TAKEN",
+	.code = 0x20004,
+	.short_desc = "Branch Taken",
+	.long_desc = "A branch instruction was taken. This could have been a conditional branch or an unconditional branch",
+},
+{
+	.name = "PM_INST_PTEG_FROM_LMEM",
+	.code = 0x4e052,
+	.short_desc = "Instruction PTEG loaded from local memory",
+	.long_desc = "Instruction PTEG loaded from local memory",
+},
+{
+	.name = "PM_GCT_NOSLOT_BR_MPRED_IC_MISS",
+	.code = 0x4001c,
+	.short_desc = "GCT empty by branch  mispredict + IC miss",
+	.long_desc = "No slot in GCT caused by branch mispredict or I cache miss",
+},
+{
+	.name = "PM_DTLB_MISS_4K",
+	.code = 0x2c05a,
+	.short_desc = "Data TLB miss for 4K page",
+	.long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_PMC4_SAVED",
+	.code = 0x30022,
+	.short_desc = "PMC4 Rewind Value saved (matched condition)",
+	.long_desc = "PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
+},
+{
+	.name = "PM_VSU1_PERMUTE_ISSUED",
+	.code = 0xb092,
+	.short_desc = "Permute VMX Instruction Issued",
+	.long_desc = "Permute VMX Instruction Issued",
+},
+{
+	.name = "PM_SLB_MISS",
+	.code = 0xd890,
+	.short_desc = "Data + Instruction SLB Miss - Total of all segment sizes",
+	.long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.",
+},
+{
+	.name = "PM_LSU1_FLUSH_LRQ",
+	.code = 0xc0ba,
+	.short_desc = "LS1 Flush: LRQ",
+	.long_desc = "Load Hit Load or Store Hit Load flush.  A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
+},
+{
+	.name = "PM_DTLB_MISS",
+	.code = 0x300fc,
+	.short_desc = "TLB reload valid",
+	.long_desc = "Data TLB misses, all page sizes.",
+},
+{
+	.name = "PM_VSU1_FRSP",
+	.code = 0xa0b6,
+	.short_desc = "Round to single precision instruction executed",
+	.long_desc = "Round to single precision instruction executed",
+},
+{
+	.name = "PM_VSU_VECTOR_DOUBLE_ISSUED",
+	.code = 0xb880,
+	.short_desc = "Double Precision vector instruction issued on Pipe0",
+	.long_desc = "Double Precision vector instruction issued on Pipe0",
+},
+{
+	.name = "PM_L2_CASTOUT_SHR",
+	.code = 0x16182,
+	.short_desc = "L2 Castouts - Shared (T, Te, Si, S)",
+	.long_desc = "An L2 line in the Shared state was castout. Total for all slices.",
+},
+{
+	.name = "PM_DATA_FROM_DL2L3_SHR",
+	.code = 0x3c044,
+	.short_desc = "Data loaded from distant L2 or L3 shared",
+	.long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load",
+},
+{
+	.name = "PM_VSU1_STF",
+	.code = 0xb08e,
+	.short_desc = "FPU store (SP or DP) issued on Pipe1",
+	.long_desc = "FPU store (SP or DP) issued on Pipe1",
+},
+{
+	.name = "PM_ST_FIN",
+	.code = 0x200f0,
+	.short_desc = "Store Instructions Finished",
+	.long_desc = "Store requests sent to the nest.",
+},
+{
+	.name = "PM_PTEG_FROM_L21_SHR",
+	.code = 0x4c056,
+	.short_desc = "PTEG loaded from another L2 on same chip shared",
+	.long_desc = "PTEG loaded from another L2 on same chip shared",
+},
+{
+	.name = "PM_L2_LOC_GUESS_WRONG",
+	.code = 0x26480,
+	.short_desc = "L2 guess loc and guess was not correct (ie data remote)",
+	.long_desc = "L2 guess loc and guess was not correct (ie data remote)",
+},
+{
+	.name = "PM_MRK_STCX_FAIL",
+	.code = 0xd08e,
+	.short_desc = "Marked STCX failed",
+	.long_desc = "A marked stcx (stwcx or stdcx) failed",
+},
+{
+	.name = "PM_LSU0_REJECT_LHS",
+	.code = 0xc0ac,
+	.short_desc = "LS0 Reject: Load Hit Store",
+	.long_desc = "Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.",
+},
+{
+	.name = "PM_IC_PREF_CANCEL_HIT",
+	.code = 0x4092,
+	.short_desc = "Prefetch Canceled due to icache hit",
+	.long_desc = "Prefetch Canceled due to icache hit",
+},
+{
+	.name = "PM_L3_PREF_BUSY",
+	.code = 0x4f080,
+	.short_desc = "Prefetch machines >= threshold (8,16,20,24)",
+	.long_desc = "Prefetch machines >= threshold (8,16,20,24)",
+},
+{
+	.name = "PM_MRK_BRU_FIN",
+	.code = 0x2003a,
+	.short_desc = "bru marked instr finish",
+	.long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.",
+},
+{
+	.name = "PM_LSU1_NCLD",
+	.code = 0xc08e,
+	.short_desc = "LS1 Non-cachable Loads counted at finish",
+	.long_desc = "A non-cacheable load was executed by Unit 0.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L31_MOD",
+	.code = 0x1e054,
+	.short_desc = "Instruction PTEG loaded from another L3 on same chip modified",
+	.long_desc = "Instruction PTEG loaded from another L3 on same chip modified",
+},
+{
+	.name = "PM_LSU_NCLD",
+	.code = 0xc88c,
+	.short_desc = "Non-cachable Loads counted at finish",
+	.long_desc = "A non-cacheable load was executed. Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_LSU_LDX",
+	.code = 0xc888,
+	.short_desc = "All Vector loads (vsx vector + vmx vector)",
+	.long_desc = "All Vector loads (vsx vector + vmx vector)",
+},
+{
+	.name = "PM_L2_LOC_GUESS_CORRECT",
+	.code = 0x16480,
+	.short_desc = "L2 guess loc and guess was correct (ie data local)",
+	.long_desc = "L2 guess loc and guess was correct (ie data local)",
+},
+{
+	.name = "PM_THRESH_TIMEO",
+	.code = 0x10038,
+	.short_desc = "Threshold  timeout  event",
+	.long_desc = "The threshold timer expired",
+},
+{
+	.name = "PM_L3_PREF_ST",
+	.code = 0xd0ae,
+	.short_desc = "L3 cache ST prefetches",
+	.long_desc = "L3 cache ST prefetches",
+},
+{
+	.name = "PM_DISP_CLB_HELD_SYNC",
+	.code = 0x2098,
+	.short_desc = "Dispatch/CLB Hold: Sync type instruction",
+	.long_desc = "Dispatch/CLB Hold: Sync type instruction",
+},
+{
+	.name = "PM_VSU_SIMPLE_ISSUED",
+	.code = 0xb894,
+	.short_desc = "Simple VMX instruction issued",
+	.long_desc = "Simple VMX instruction issued",
+},
+{
+	.name = "PM_VSU1_SINGLE",
+	.code = 0xa0aa,
+	.short_desc = "FPU single precision",
+	.long_desc = "VSU1 executed single precision instruction",
+},
+{
+	.name = "PM_DATA_TABLEWALK_CYC",
+	.code = 0x3001a,
+	.short_desc = "Data Tablewalk Active",
+	.long_desc = "Cycles a translation tablewalk is active.  While a tablewalk is active any request attempting to access the TLB will be rejected and retried.",
+},
+{
+	.name = "PM_L2_RC_ST_DONE",
+	.code = 0x36380,
+	.short_desc = "RC did st to line that was Tx or Sx",
+	.long_desc = "RC did st to line that was Tx or Sx",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L21_MOD",
+	.code = 0x3d056,
+	.short_desc = "Marked PTEG loaded from another L2 on same chip modified",
+	.long_desc = "Marked PTEG loaded from another L2 on same chip modified",
+},
+{
+	.name = "PM_LARX_LSU1",
+	.code = 0xc096,
+	.short_desc = "ls1 Larx Finished",
+	.long_desc = "A larx (lwarx or ldarx) was executed on side 1 ",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RMEM",
+	.code = 0x3d042,
+	.short_desc = "Marked data loaded from remote memory",
+	.long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.",
+},
+{
+	.name = "PM_DISP_CLB_HELD",
+	.code = 0x2090,
+	.short_desc = "CLB Hold: Any Reason",
+	.long_desc = "CLB Hold: Any Reason",
+},
+{
+	.name = "PM_DERAT_MISS_4K",
+	.code = 0x1c05c,
+	.short_desc = "DERAT misses for 4K page",
+	.long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_L2_RCLD_DISP_FAIL_ADDR",
+	.code = 0x16282,
+	.short_desc = " L2  RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+	.long_desc = " L2  RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+},
+{
+	.name = "PM_SEG_EXCEPTION",
+	.code = 0x28a4,
+	.short_desc = "ISEG + DSEG Exception",
+	.long_desc = "ISEG + DSEG Exception",
+},
+{
+	.name = "PM_FLUSH_DISP_SB",
+	.code = 0x208c,
+	.short_desc = "Dispatch Flush: Scoreboard",
+	.long_desc = "Dispatch Flush: Scoreboard",
+},
+{
+	.name = "PM_L2_DC_INV",
+	.code = 0x26182,
+	.short_desc = "Dcache invalidates from L2 ",
+	.long_desc = "The L2 invalidated a line in processor's data cache.  This is caused by the L2 line being cast out or invalidated. Total for all slices",
+},
+{
+	.name = "PM_PTEG_FROM_DL2L3_MOD",
+	.code = 0x4c054,
+	.short_desc = "PTEG loaded from distant L2 or L3 modified",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a demand load or store.",
+},
+{
+	.name = "PM_DSEG",
+	.code = 0x20a6,
+	.short_desc = "DSEG Exception",
+	.long_desc = "DSEG Exception",
+},
+{
+	.name = "PM_BR_PRED_LSTACK",
+	.code = 0x40a2,
+	.short_desc = "Link Stack Predictions",
+	.long_desc = "The target address of a Branch to Link instruction was predicted by the link stack.",
+},
+{
+	.name = "PM_VSU0_STF",
+	.code = 0xb08c,
+	.short_desc = "FPU store (SP or DP) issued on Pipe0",
+	.long_desc = "FPU store (SP or DP) issued on Pipe0",
+},
+{
+	.name = "PM_LSU_FX_FIN",
+	.code = 0x10066,
+	.short_desc = "LSU Finished a FX operation  (up to 2 per cycle)",
+	.long_desc = "LSU Finished a FX operation  (up to 2 per cycle)",
+},
+{
+	.name = "PM_DERAT_MISS_16M",
+	.code = 0x3c05c,
+	.short_desc = "DERAT misses for 16M page",
+	.long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_DL2L3_MOD",
+	.code = 0x4d054,
+	.short_desc = "Marked PTEG loaded from distant L2 or L3 modified",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a marked load or store.",
+},
+{
+	.name = "PM_GCT_UTIL_11_PLUS_SLOTS",
+	.code = 0x20a2,
+	.short_desc = "GCT Utilization 11+ entries",
+	.long_desc = "GCT Utilization 11+ entries",
+},
+{
+	.name = "PM_INST_FROM_L3",
+	.code = 0x14048,
+	.short_desc = "Instruction fetched from L3",
+	.long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_MRK_IFU_FIN",
+	.code = 0x3003a,
+	.short_desc = "IFU non-branch marked instruction finished",
+	.long_desc = "The Instruction Fetch Unit finished a marked instruction.",
+},
+{
+	.name = "PM_ITLB_MISS",
+	.code = 0x400fc,
+	.short_desc = "ITLB Reloaded (always zero on POWER6)",
+	.long_desc = "A TLB miss for an Instruction Fetch has occurred",
+},
+{
+	.name = "PM_VSU_STF",
+	.code = 0xb88c,
+	.short_desc = "FPU store (SP or DP) issued on Pipe0",
+	.long_desc = "FPU store (SP or DP) issued on Pipe0",
+},
+{
+	.name = "PM_LSU_FLUSH_UST",
+	.code = 0xc8b4,
+	.short_desc = "Flush: Unaligned Store",
+	.long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary).  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_L2_LDST_MISS",
+	.code = 0x26880,
+	.short_desc = "Data Load+Store Miss",
+	.long_desc = "Data Load+Store Miss",
+},
+{
+	.name = "PM_FXU1_FIN",
+	.code = 0x40004,
+	.short_desc = "FXU1 Finished",
+	.long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
+},
+{
+	.name = "PM_SHL_DEALLOCATED",
+	.code = 0x5080,
+	.short_desc = "SHL Table entry deallocated",
+	.long_desc = "SHL Table entry deallocated",
+},
+{
+	.name = "PM_L2_SN_M_WR_DONE",
+	.code = 0x46382,
+	.short_desc = "SNP dispatched for a write and was M",
+	.long_desc = "SNP dispatched for a write and was M",
+},
+{
+	.name = "PM_LSU_REJECT_SET_MPRED",
+	.code = 0xc8a8,
+	.short_desc = "Reject: Set Predict Wrong",
+	.long_desc = "The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1",
+},
+{
+	.name = "PM_L3_PREF_LD",
+	.code = 0xd0ac,
+	.short_desc = "L3 cache LD prefetches",
+	.long_desc = "L3 cache LD prefetches",
+},
+{
+	.name = "PM_L2_SN_M_RD_DONE",
+	.code = 0x46380,
+	.short_desc = "SNP dispatched for a read and was M",
+	.long_desc = "SNP dispatched for a read and was M",
+},
+{
+	.name = "PM_MRK_DERAT_MISS_16G",
+	.code = 0x4d05c,
+	.short_desc = "Marked DERAT misses for 16G page",
+	.long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_VSU_FCONV",
+	.code = 0xa8b0,
+	.short_desc = "Convert instruction executed",
+	.long_desc = "Convert instruction executed",
+},
+{
+	.name = "PM_ANY_THRD_RUN_CYC",
+	.code = 0x100fa,
+	.short_desc = "One of threads in run_cycles ",
+	.long_desc = "One of threads in run_cycles ",
+},
+{
+	.name = "PM_LSU_LMQ_FULL_CYC",
+	.code = 0xd0a4,
+	.short_desc = "LMQ full",
+	.long_desc = "The Load Miss Queue was full.",
+},
+{
+	.name = "PM_MRK_LSU_REJECT_LHS",
+	.code = 0xd082,
+	.short_desc = " Reject(marked): Load Hit Store",
+	.long_desc = "The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully",
+},
+{
+	.name = "PM_MRK_LD_MISS_L1_CYC",
+	.code = 0x4003e,
+	.short_desc = "L1 data load miss cycles",
+	.long_desc = "L1 data load miss cycles",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L2_CYC",
+	.code = 0x20020,
+	.short_desc = "Marked ld latency Data source 0000 (L2 hit)",
+	.long_desc = "Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+	.name = "PM_INST_IMC_MATCH_DISP",
+	.code = 0x30016,
+	.short_desc = "IMC Matches dispatched",
+	.long_desc = "IMC Matches dispatched",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RMEM_CYC",
+	.code = 0x4002c,
+	.short_desc = "Marked ld latency Data source 1101  (Memory same 4 chip node)",
+	.long_desc = "Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+	.name = "PM_VSU0_SIMPLE_ISSUED",
+	.code = 0xb094,
+	.short_desc = "Simple VMX instruction issued",
+	.long_desc = "Simple VMX instruction issued",
+},
+{
+	.name = "PM_CMPLU_STALL_DIV",
+	.code = 0x40014,
+	.short_desc = "Completion stall caused by DIV instruction",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_RL2L3_SHR",
+	.code = 0x2d054,
+	.short_desc = "Marked PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.",
+},
+{
+	.name = "PM_VSU_FMA_DOUBLE",
+	.code = 0xa890,
+	.short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
+	.long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
+},
+{
+	.name = "PM_VSU_4FLOP",
+	.code = 0xa89c,
+	.short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+	.long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_VSU1_FIN",
+	.code = 0xa0be,
+	.short_desc = "VSU1 Finished an instruction",
+	.long_desc = "VSU1 Finished an instruction",
+},
+{
+	.name = "PM_NEST_PAIR1_AND",
+	.code = 0x20883,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 AND",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 AND",
+},
+{
+	.name = "PM_INST_PTEG_FROM_RL2L3_MOD",
+	.code = 0x1e052,
+	.short_desc = "Instruction PTEG loaded from remote L2 or L3 modified",
+	.long_desc = "Instruction PTEG loaded from remote L2 or L3 modified",
+},
+{
+	.name = "PM_RUN_CYC",
+	.code = 0x200f4,
+	.short_desc = "Run_cycles",
+	.long_desc = "Processor Cycles gated by the run latch.  Operating systems use the run latch to indicate when they are doing useful work.  The run latch is typically cleared in the OS idle loop.  Gating by the run latch filters out the idle loop.",
+},
+{
+	.name = "PM_PTEG_FROM_RMEM",
+	.code = 0x3c052,
+	.short_desc = "PTEG loaded from remote memory",
+	.long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.",
+},
+{
+	.name = "PM_LSU_LRQ_S0_VALID",
+	.code = 0xd09e,
+	.short_desc = "Slot 0 of LRQ valid",
+	.long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the LRQ is split between the two threads (16 entries each).",
+},
+{
+	.name = "PM_LSU0_LDF",
+	.code = 0xc084,
+	.short_desc = "LS0 Scalar  Loads",
+	.long_desc = "A floating point load was executed by LSU0",
+},
+{
+	.name = "PM_FLUSH_COMPLETION",
+	.code = 0x30012,
+	.short_desc = "Completion Flush",
+	.long_desc = "Completion Flush",
+},
+{
+	.name = "PM_ST_MISS_L1",
+	.code = 0x300f0,
+	.short_desc = "L1 D cache store misses",
+	.long_desc = "A store missed the dcache.  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_L2_NODE_PUMP",
+	.code = 0x36480,
+	.short_desc = "RC req that was a local (aka node) pump attempt",
+	.long_desc = "RC req that was a local (aka node) pump attempt",
+},
+{
+	.name = "PM_INST_FROM_DL2L3_SHR",
+	.code = 0x34044,
+	.short_desc = "Instruction fetched from distant L2 or L3 shared",
+	.long_desc = "An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_MRK_STALL_CMPLU_CYC",
+	.code = 0x3003e,
+	.short_desc = "Marked Group Completion Stall cycles ",
+	.long_desc = "Marked Group Completion Stall cycles ",
+},
+{
+	.name = "PM_VSU1_DENORM",
+	.code = 0xa0ae,
+	.short_desc = "FPU denorm operand",
+	.long_desc = "VSU1 received denormalized data",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L31_SHR_CYC",
+	.code = 0x20026,
+	.short_desc = "Marked ld latency Data source 0110 (L3.1 S) ",
+	.long_desc = "Marked load latency Data source 0110 (L3.1 S) ",
+},
+{
+	.name = "PM_NEST_PAIR0_ADD",
+	.code = 0x10881,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 ADD",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 ADD",
+},
+{
+	.name = "PM_INST_FROM_L3MISS",
+	.code = 0x24048,
+	.short_desc = "Instruction fetched missed L3",
+	.long_desc = "An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.",
+},
+{
+	.name = "PM_EE_OFF_EXT_INT",
+	.code = 0x2080,
+	.short_desc = "ee off and external interrupt",
+	.long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_DMEM",
+	.code = 0x2e052,
+	.short_desc = "Instruction PTEG loaded from distant memory",
+	.long_desc = "Instruction PTEG loaded from distant memory",
+},
+{
+	.name = "PM_INST_FROM_DL2L3_MOD",
+	.code = 0x3404c,
+	.short_desc = "Instruction fetched from distant L2 or L3 modified",
+	.long_desc = "An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_PMC6_OVERFLOW",
+	.code = 0x30024,
+	.short_desc = "Overflow from counter 6",
+	.long_desc = "Overflows from PMC6 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_VSU_2FLOP_DOUBLE",
+	.code = 0xa88c,
+	.short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
+	.long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
+},
+{
+	.name = "PM_TLB_MISS",
+	.code = 0x20066,
+	.short_desc = "TLB Miss (I + D)",
+	.long_desc = "Total of Data TLB mises + Instruction TLB misses",
+},
+{
+	.name = "PM_FXU_BUSY",
+	.code = 0x2000e,
+	.short_desc = "fxu0 busy and fxu1 busy.",
+	.long_desc = "Cycles when both FXU0 and FXU1 are busy.",
+},
+{
+	.name = "PM_L2_RCLD_DISP_FAIL_OTHER",
+	.code = 0x26280,
+	.short_desc = " L2  RC load dispatch attempt failed due to other reasons",
+	.long_desc = " L2  RC load dispatch attempt failed due to other reasons",
+},
+{
+	.name = "PM_LSU_REJECT_LMQ_FULL",
+	.code = 0xc8a4,
+	.short_desc = "Reject: LMQ Full (LHR)",
+	.long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.",
+},
+{
+	.name = "PM_IC_RELOAD_SHR",
+	.code = 0x4096,
+	.short_desc = "Reloading line to be shared between the threads",
+	.long_desc = "An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.",
+},
+{
+	.name = "PM_GRP_MRK",
+	.code = 0x10031,
+	.short_desc = "IDU Marked Instruction",
+	.long_desc = "A group was sampled (marked).  The group is called a marked group.  One instruction within the group is tagged for detailed monitoring.  The sampled instruction is called a marked instructions.  Events associated with the marked instruction are annotated with the marked term.",
+},
+{
+	.name = "PM_MRK_ST_NEST",
+	.code = 0x20034,
+	.short_desc = "marked store sent to Nest",
+	.long_desc = "A sampled store has been sent to the memory subsystem",
+},
+{
+	.name = "PM_VSU1_FSQRT_FDIV",
+	.code = 0xa08a,
+	.short_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+	.long_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+},
+{
+	.name = "PM_LSU0_FLUSH_LRQ",
+	.code = 0xc0b8,
+	.short_desc = "LS0 Flush: LRQ",
+	.long_desc = "Load Hit Load or Store Hit Load flush.  A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
+},
+{
+	.name = "PM_LARX_LSU0",
+	.code = 0xc094,
+	.short_desc = "ls0 Larx Finished",
+	.long_desc = "A larx (lwarx or ldarx) was executed on side 0 ",
+},
+{
+	.name = "PM_IBUF_FULL_CYC",
+	.code = 0x4084,
+	.short_desc = "Cycles No room in ibuff",
+	.long_desc = "Cycles with the Instruction Buffer was full.  The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
+	.code = 0x2002a,
+	.short_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)",
+	.long_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)",
+},
+{
+	.name = "PM_LSU_DC_PREF_STREAM_ALLOC",
+	.code = 0xd8a8,
+	.short_desc = "D cache new prefetch stream allocated",
+	.long_desc = "D cache new prefetch stream allocated",
+},
+{
+	.name = "PM_GRP_MRK_CYC",
+	.code = 0x10030,
+	.short_desc = "cycles IDU marked instruction before dispatch",
+	.long_desc = "cycles IDU marked instruction before dispatch",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
+	.code = 0x20028,
+	.short_desc = "Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S)",
+	.long_desc = "Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)",
+},
+{
+	.name = "PM_L2_GLOB_GUESS_CORRECT",
+	.code = 0x16482,
+	.short_desc = "L2 guess glb and guess was correct (ie data remote)",
+	.long_desc = "L2 guess glb and guess was correct (ie data remote)",
+},
+{
+	.name = "PM_LSU_REJECT_LHS",
+	.code = 0xc8ac,
+	.short_desc = "Reject: Load Hit Store",
+	.long_desc = "The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1",
+},
+{
+	.name = "PM_MRK_DATA_FROM_LMEM",
+	.code = 0x3d04a,
+	.short_desc = "Marked data loaded from local memory",
+	.long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L3",
+	.code = 0x2e050,
+	.short_desc = "Instruction PTEG loaded from L3",
+	.long_desc = "Instruction PTEG loaded from L3",
+},
+{
+	.name = "PM_FREQ_DOWN",
+	.code = 0x3000c,
+	.short_desc = "Frequency is being slewed down due to Power Management",
+	.long_desc = "Processor frequency was slowed down due to power management",
+},
+{
+	.name = "PM_PB_RETRY_NODE_PUMP",
+	.code = 0x30081,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit0",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit0",
+},
+{
+	.name = "PM_INST_FROM_RL2L3_SHR",
+	.code = 0x1404c,
+	.short_desc = "Instruction fetched from remote L2 or L3 shared",
+	.long_desc = "An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_MRK_INST_ISSUED",
+	.code = 0x10032,
+	.short_desc = "Marked instruction issued",
+	.long_desc = "A marked instruction was issued to an execution unit.",
+},
+{
+	.name = "PM_PTEG_FROM_L3MISS",
+	.code = 0x2c058,
+	.short_desc = "PTEG loaded from L3 miss",
+	.long_desc = " Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.",
+},
+{
+	.name = "PM_RUN_PURR",
+	.code = 0x400f4,
+	.short_desc = "Run_PURR",
+	.long_desc = "The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. ",
+},
+{
+	.name = "PM_MRK_GRP_IC_MISS",
+	.code = 0x40038,
+	.short_desc = "Marked group experienced  I cache miss",
+	.long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L3",
+	.code = 0x1d048,
+	.short_desc = "Marked data loaded from L3",
+	.long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.",
+},
+{
+	.name = "PM_CMPLU_STALL_DCACHE_MISS",
+	.code = 0x20016,
+	.short_desc = "Completion stall caused by D cache miss",
+	.long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.",
+},
+{
+	.name = "PM_PTEG_FROM_RL2L3_SHR",
+	.code = 0x2c054,
+	.short_desc = "PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.",
+},
+{
+	.name = "PM_LSU_FLUSH_LRQ",
+	.code = 0xc8b8,
+	.short_desc = "Flush: LRQ",
+	.long_desc = "Load Hit Load or Store Hit Load flush.  A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.  Combined Unit 0 + 1.",
+},
+{
+	.name = "PM_MRK_DERAT_MISS_64K",
+	.code = 0x2d05c,
+	.short_desc = "Marked DERAT misses for 64K page",
+	.long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_INST_PTEG_FROM_DL2L3_MOD",
+	.code = 0x4e054,
+	.short_desc = "Instruction PTEG loaded from distant L2 or L3 modified",
+	.long_desc = "Instruction PTEG loaded from distant L2 or L3 modified",
+},
+{
+	.name = "PM_L2_ST_MISS",
+	.code = 0x26082,
+	.short_desc = "Data Store Miss",
+	.long_desc = "Data Store Miss",
+},
+{
+	.name = "PM_LWSYNC",
+	.code = 0xd094,
+	.short_desc = "lwsync count (easier to use than IMC)",
+	.long_desc = "lwsync count (easier to use than IMC)",
+},
+{
+	.name = "PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE",
+	.code = 0xd0bc,
+	.short_desc = "LS0 Dcache Strided prefetch stream confirmed",
+	.long_desc = "LS0 Dcache Strided prefetch stream confirmed",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L21_SHR",
+	.code = 0x4d056,
+	.short_desc = "Marked PTEG loaded from another L2 on same chip shared",
+	.long_desc = "Marked PTEG loaded from another L2 on same chip shared",
+},
+{
+	.name = "PM_MRK_LSU_FLUSH_LRQ",
+	.code = 0xd088,
+	.short_desc = "Flush: (marked) LRQ",
+	.long_desc = "Load Hit Load or Store Hit Load flush.  A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
+},
+{
+	.name = "PM_INST_IMC_MATCH_CMPL",
+	.code = 0x100f0,
+	.short_desc = "IMC Match Count",
+	.long_desc = "Number of instructions resulting from the marked instructions expansion that completed.",
+},
+{
+	.name = "PM_NEST_PAIR3_AND",
+	.code = 0x40883,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 AND",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 AND",
+},
+{
+	.name = "PM_PB_RETRY_SYS_PUMP",
+	.code = 0x40081,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit0",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit0",
+},
+{
+	.name = "PM_MRK_INST_FIN",
+	.code = 0x30030,
+	.short_desc = "marked instr finish any unit ",
+	.long_desc = "One of the execution units finished a marked instruction.  Instructions that finish may not necessary complete",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_DL2L3_SHR",
+	.code = 0x3d054,
+	.short_desc = "Marked PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.",
+},
+{
+	.name = "PM_INST_FROM_L31_MOD",
+	.code = 0x14044,
+	.short_desc = "Instruction fetched from another L3 on same chip modified",
+	.long_desc = "Instruction fetched from another L3 on same chip modified",
+},
+{
+	.name = "PM_MRK_DTLB_MISS_64K",
+	.code = 0x3d05e,
+	.short_desc = "Marked Data TLB misses for 64K page",
+	.long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_LSU_FIN",
+	.code = 0x30066,
+	.short_desc = "LSU Finished an instruction (up to 2 per cycle)",
+	.long_desc = "LSU Finished an instruction (up to 2 per cycle)",
+},
+{
+	.name = "PM_MRK_LSU_REJECT",
+	.code = 0x40064,
+	.short_desc = "LSU marked reject (up to 2 per cycle)",
+	.long_desc = "LSU marked reject (up to 2 per cycle)",
+},
+{
+	.name = "PM_L2_CO_FAIL_BUSY",
+	.code = 0x16382,
+	.short_desc = " L2  RC Cast Out dispatch attempt failed due to all CO machines busy",
+	.long_desc = " L2  RC Cast Out dispatch attempt failed due to all CO machines busy",
+},
+{
+	.name = "PM_MEM0_WQ_DISP",
+	.code = 0x40083,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit1",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 Bit1",
+},
+{
+	.name = "PM_DATA_FROM_L31_MOD",
+	.code = 0x1c044,
+	.short_desc = "Data loaded from another L3 on same chip modified",
+	.long_desc = "Data loaded from another L3 on same chip modified",
+},
+{
+	.name = "PM_THERMAL_WARN",
+	.code = 0x10016,
+	.short_desc = "Processor in Thermal Warning",
+	.long_desc = "Processor in Thermal Warning",
+},
+{
+	.name = "PM_VSU0_4FLOP",
+	.code = 0xa09c,
+	.short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+	.long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_BR_MPRED_CCACHE",
+	.code = 0x40a4,
+	.short_desc = "Branch Mispredict due to Count Cache prediction",
+	.long_desc = "A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
+},
+{
+	.name = "PM_CMPLU_STALL_IFU",
+	.code = 0x4004c,
+	.short_desc = "Completion stall due to IFU ",
+	.long_desc = "Completion stall due to IFU ",
+},
+{
+	.name = "PM_L1_DEMAND_WRITE",
+	.code = 0x408c,
+	.short_desc = "Instruction Demand sectors wriittent into IL1",
+	.long_desc = "Instruction Demand sectors wriittent into IL1",
+},
+{
+	.name = "PM_FLUSH_BR_MPRED",
+	.code = 0x2084,
+	.short_desc = "Flush caused by branch mispredict",
+	.long_desc = "A flush was caused by a branch mispredict.",
+},
+{
+	.name = "PM_MRK_DTLB_MISS_16G",
+	.code = 0x1d05e,
+	.short_desc = "Marked Data TLB misses for 16G page",
+	.long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_DMEM",
+	.code = 0x2d052,
+	.short_desc = "Marked PTEG loaded from distant memory",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.",
+},
+{
+	.name = "PM_L2_RCST_DISP",
+	.code = 0x36280,
+	.short_desc = " L2  RC store dispatch attempt",
+	.long_desc = " L2  RC store dispatch attempt",
+},
+{
+	.name = "PM_CMPLU_STALL",
+	.code = 0x4000a,
+	.short_desc = "No groups completed, GCT not empty",
+	.long_desc = "No groups completed, GCT not empty",
+},
+{
+	.name = "PM_LSU_PARTIAL_CDF",
+	.code = 0xc0aa,
+	.short_desc = "A partial cacheline was returned from the L3",
+	.long_desc = "A partial cacheline was returned from the L3",
+},
+{
+	.name = "PM_DISP_CLB_HELD_SB",
+	.code = 0x20a8,
+	.short_desc = "Dispatch/CLB Hold: Scoreboard",
+	.long_desc = "Dispatch/CLB Hold: Scoreboard",
+},
+{
+	.name = "PM_VSU0_FMA_DOUBLE",
+	.code = 0xa090,
+	.short_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)",
+	.long_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)",
+},
+{
+	.name = "PM_FXU0_BUSY_FXU1_IDLE",
+	.code = 0x3000e,
+	.short_desc = "fxu0 busy and fxu1 idle",
+	.long_desc = "FXU0 is busy while FXU1 was idle",
+},
+{
+	.name = "PM_IC_DEMAND_CYC",
+	.code = 0x10018,
+	.short_desc = "Cycles when a demand ifetch was pending",
+	.long_desc = "Cycles when a demand ifetch was pending",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L21_SHR",
+	.code = 0x3d04e,
+	.short_desc = "Marked data loaded from another L2 on same chip shared",
+	.long_desc = "Marked data loaded from another L2 on same chip shared",
+},
+{
+	.name = "PM_MRK_LSU_FLUSH_UST",
+	.code = 0xd086,
+	.short_desc = "Flush: (marked) Unaligned Store",
+	.long_desc = "A marked store was flushed because it was unaligned",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L3MISS",
+	.code = 0x2e058,
+	.short_desc = "Instruction PTEG loaded from L3 miss",
+	.long_desc = "Instruction PTEG loaded from L3 miss",
+},
+{
+	.name = "PM_VSU_DENORM",
+	.code = 0xa8ac,
+	.short_desc = "Vector or Scalar denorm operand",
+	.long_desc = "Vector or Scalar denorm operand",
+},
+{
+	.name = "PM_MRK_LSU_PARTIAL_CDF",
+	.code = 0xd080,
+	.short_desc = "A partial cacheline was returned from the L3 for a marked load",
+	.long_desc = "A partial cacheline was returned from the L3 for a marked load",
+},
+{
+	.name = "PM_INST_FROM_L21_SHR",
+	.code = 0x3404e,
+	.short_desc = "Instruction fetched from another L2 on same chip shared",
+	.long_desc = "Instruction fetched from another L2 on same chip shared",
+},
+{
+	.name = "PM_IC_PREF_WRITE",
+	.code = 0x408e,
+	.short_desc = "Instruction prefetch written into IL1",
+	.long_desc = "Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.",
+},
+{
+	.name = "PM_BR_PRED",
+	.code = 0x409c,
+	.short_desc = "Branch Predictions made",
+	.long_desc = "A branch prediction was made. This could have been a target prediction, a condition prediction, or both",
+},
+{
+	.name = "PM_INST_FROM_DMEM",
+	.code = 0x1404a,
+	.short_desc = "Instruction fetched from distant memory",
+	.long_desc = "An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_IC_PREF_CANCEL_ALL",
+	.code = 0x4890,
+	.short_desc = "Prefetch Canceled due to page boundary or icache hit",
+	.long_desc = "Prefetch Canceled due to page boundary or icache hit",
+},
+{
+	.name = "PM_LSU_DC_PREF_STREAM_CONFIRM",
+	.code = 0xd8b4,
+	.short_desc = "Dcache new prefetch stream confirmed",
+	.long_desc = "Dcache new prefetch stream confirmed",
+},
+{
+	.name = "PM_MRK_LSU_FLUSH_SRQ",
+	.code = 0xd08a,
+	.short_desc = "Flush: (marked) SRQ",
+	.long_desc = "Load Hit Store flush.  A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions. ",
+},
+{
+	.name = "PM_MRK_FIN_STALL_CYC",
+	.code = 0x1003c,
+	.short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ",
+	.long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ",
+},
+{
+	.name = "PM_L2_RCST_DISP_FAIL_OTHER",
+	.code = 0x46280,
+	.short_desc = " L2  RC store dispatch attempt failed due to other reasons",
+	.long_desc = " L2  RC store dispatch attempt failed due to other reasons",
+},
+{
+	.name = "PM_VSU1_DD_ISSUED",
+	.code = 0xb098,
+	.short_desc = "64BIT Decimal Issued on Pipe1",
+	.long_desc = "64BIT Decimal Issued on Pipe1",
+},
+{
+	.name = "PM_PTEG_FROM_L31_SHR",
+	.code = 0x2c056,
+	.short_desc = "PTEG loaded from another L3 on same chip shared",
+	.long_desc = "PTEG loaded from another L3 on same chip shared",
+},
+{
+	.name = "PM_DATA_FROM_L21_SHR",
+	.code = 0x3c04e,
+	.short_desc = "Data loaded from another L2 on same chip shared",
+	.long_desc = "Data loaded from another L2 on same chip shared",
+},
+{
+	.name = "PM_LSU0_NCLD",
+	.code = 0xc08c,
+	.short_desc = "LS0 Non-cachable Loads counted at finish",
+	.long_desc = "A non-cacheable load was executed by unit 0.",
+},
+{
+	.name = "PM_VSU1_4FLOP",
+	.code = 0xa09e,
+	.short_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+	.long_desc = "four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)",
+},
+{
+	.name = "PM_VSU1_8FLOP",
+	.code = 0xa0a2,
+	.short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+	.long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+},
+{
+	.name = "PM_VSU_8FLOP",
+	.code = 0xa8a0,
+	.short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+	.long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+},
+{
+	.name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+	.code = 0x2003e,
+	.short_desc = "LSU empty (lmq and srq empty)",
+	.long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)",
+},
+{
+	.name = "PM_DTLB_MISS_64K",
+	.code = 0x3c05e,
+	.short_desc = "Data TLB miss for 64K page",
+	.long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_THRD_CONC_RUN_INST",
+	.code = 0x300f4,
+	.short_desc = "Concurrent Run Instructions",
+	.long_desc = "Instructions completed by this thread when both threads had their run latches set.",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L2",
+	.code = 0x1d050,
+	.short_desc = "Marked PTEG loaded from L2",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.",
+},
+{
+	.name = "PM_PB_SYS_PUMP",
+	.code = 0x20081,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit0",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit0",
+},
+{
+	.name = "PM_VSU_FIN",
+	.code = 0xa8bc,
+	.short_desc = "VSU0 Finished an instruction",
+	.long_desc = "VSU0 Finished an instruction",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L31_MOD",
+	.code = 0x1d044,
+	.short_desc = "Marked data loaded from another L3 on same chip modified",
+	.long_desc = "Marked data loaded from another L3 on same chip modified",
+},
+{
+	.name = "PM_THRD_PRIO_0_1_CYC",
+	.code = 0x40b0,
+	.short_desc = " Cycles thread running at priority level 0 or 1",
+	.long_desc = " Cycles thread running at priority level 0 or 1",
+},
+{
+	.name = "PM_DERAT_MISS_64K",
+	.code = 0x2c05c,
+	.short_desc = "DERAT misses for 64K page",
+	.long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.",
+},
+{
+	.name = "PM_PMC2_REWIND",
+	.code = 0x30020,
+	.short_desc = "PMC2 Rewind Event (did not match condition)",
+	.long_desc = "PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.",
+},
+{
+	.name = "PM_INST_FROM_L2",
+	.code = 0x14040,
+	.short_desc = "Instruction fetched from L2",
+	.long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_GRP_BR_MPRED_NONSPEC",
+	.code = 0x1000a,
+	.short_desc = "Group experienced non-speculative branch redirect",
+	.long_desc = "Group experienced non-speculative branch redirect",
+},
+{
+	.name = "PM_INST_DISP",
+	.code = 0x200f2,
+	.short_desc = "# PPC Dispatched",
+	.long_desc = "Number of PowerPC instructions successfully dispatched.",
+},
+{
+	.name = "PM_MEM0_RD_CANCEL_TOTAL",
+	.code = 0x30083,
+	.short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit1",
+	.long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 Bit1",
+},
+{
+	.name = "PM_LSU0_DC_PREF_STREAM_CONFIRM",
+	.code = 0xd0b4,
+	.short_desc = "LS0 Dcache prefetch stream confirmed",
+	.long_desc = "LS0 Dcache prefetch stream confirmed",
+},
+{
+	.name = "PM_L1_DCACHE_RELOAD_VALID",
+	.code = 0x300f6,
+	.short_desc = "L1 reload data source valid",
+	.long_desc = "The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.",
+},
+{
+	.name = "PM_VSU_SCALAR_DOUBLE_ISSUED",
+	.code = 0xb888,
+	.short_desc = "Double Precision scalar instruction issued on Pipe0",
+	.long_desc = "Double Precision scalar instruction issued on Pipe0",
+},
+{
+	.name = "PM_L3_PREF_HIT",
+	.code = 0x3f080,
+	.short_desc = "L3 Prefetch Directory Hit",
+	.long_desc = "L3 Prefetch Directory Hit",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L31_MOD",
+	.code = 0x1d054,
+	.short_desc = "Marked PTEG loaded from another L3 on same chip modified",
+	.long_desc = "Marked PTEG loaded from another L3 on same chip modified",
+},
+{
+	.name = "PM_CMPLU_STALL_STORE",
+	.code = 0x2004a,
+	.short_desc = "Completion stall due to store instruction",
+	.long_desc = "Completion stall due to store instruction",
+},
+{
+	.name = "PM_MRK_FXU_FIN",
+	.code = 0x20038,
+	.short_desc = "fxu marked  instr finish",
+	.long_desc = "One of the Fixed Point Units finished a marked instruction.  Instructions that finish may not necessary complete.",
+},
+{
+	.name = "PM_PMC4_OVERFLOW",
+	.code = 0x10010,
+	.short_desc = "Overflow from counter 4",
+	.long_desc = "Overflows from PMC4 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+	.name = "PM_MRK_PTEG_FROM_L3",
+	.code = 0x2d050,
+	.short_desc = "Marked PTEG loaded from L3",
+	.long_desc = "A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.",
+},
+{
+	.name = "PM_LSU0_LMQ_LHR_MERGE",
+	.code = 0xd098,
+	.short_desc = "LS0  Load Merged with another cacheline request",
+	.long_desc = "LS0  Load Merged with another cacheline request",
+},
+{
+	.name = "PM_BTAC_HIT",
+	.code = 0x508a,
+	.short_desc = "BTAC Correct Prediction",
+	.long_desc = "BTAC Correct Prediction",
+},
+{
+	.name = "PM_L3_RD_BUSY",
+	.code = 0x4f082,
+	.short_desc = "Rd machines busy >= threshold (2,4,6,8)",
+	.long_desc = "Rd machines busy >= threshold (2,4,6,8)",
+},
+{
+	.name = "PM_LSU0_L1_SW_PREF",
+	.code = 0xc09c,
+	.short_desc = "LSU0 Software L1 Prefetches, including SW Transient Prefetches",
+	.long_desc = "LSU0 Software L1 Prefetches, including SW Transient Prefetches",
+},
+{
+	.name = "PM_INST_FROM_L2MISS",
+	.code = 0x44048,
+	.short_desc = "Instruction fetched missed L2",
+	.long_desc = "An instruction fetch group was fetched from beyond the local L2.",
+},
+{
+	.name = "PM_LSU0_DC_PREF_STREAM_ALLOC",
+	.code = 0xd0a8,
+	.short_desc = "LS0 D cache new prefetch stream allocated",
+	.long_desc = "LS0 D cache new prefetch stream allocated",
+},
+{
+	.name = "PM_L2_ST",
+	.code = 0x16082,
+	.short_desc = "Data Store Count",
+	.long_desc = "Data Store Count",
+},
+{
+	.name = "PM_VSU0_DENORM",
+	.code = 0xa0ac,
+	.short_desc = "FPU denorm operand",
+	.long_desc = "VSU0 received denormalized data",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DL2L3_SHR",
+	.code = 0x3d044,
+	.short_desc = "Marked data loaded from distant L2 or L3 shared",
+	.long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.",
+},
+{
+	.name = "PM_BR_PRED_CR_TA",
+	.code = 0x48aa,
+	.short_desc = "Branch predict - taken/not taken and target",
+	.long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.",
+},
+{
+	.name = "PM_VSU0_FCONV",
+	.code = 0xa0b0,
+	.short_desc = "Convert instruction executed",
+	.long_desc = "Convert instruction executed",
+},
+{
+	.name = "PM_MRK_LSU_FLUSH_ULD",
+	.code = 0xd084,
+	.short_desc = "Flush: (marked) Unaligned Load",
+	.long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)",
+},
+{
+	.name = "PM_BTAC_MISS",
+	.code = 0x5088,
+	.short_desc = "BTAC Mispredicted",
+	.long_desc = "BTAC Mispredicted",
+},
+{
+	.name = "PM_MRK_LD_MISS_EXPOSED_CYC_COUNT",
+	.code = 0x1003f,
+	.short_desc = "Marked Load exposed Miss (use edge detect to count #)",
+	.long_desc = "Marked Load exposed Miss (use edge detect to count #)",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L2",
+	.code = 0x1d040,
+	.short_desc = "Marked data loaded from L2",
+	.long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.",
+},
+{
+	.name = "PM_LSU_DCACHE_RELOAD_VALID",
+	.code = 0xd0a2,
+	.short_desc = "count per sector of lines reloaded in L1 (demand + prefetch) ",
+	.long_desc = "count per sector of lines reloaded in L1 (demand + prefetch) ",
+},
+{
+	.name = "PM_VSU_FMA",
+	.code = 0xa884,
+	.short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
+	.long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
+},
+{
+	.name = "PM_LSU0_FLUSH_SRQ",
+	.code = 0xc0bc,
+	.short_desc = "LS0 Flush: SRQ",
+	.long_desc = "Load Hit Store flush.  A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions. ",
+},
+{
+	.name = "PM_LSU1_L1_PREF",
+	.code = 0xd0ba,
+	.short_desc = " LS1 L1 cache data prefetches",
+	.long_desc = " LS1 L1 cache data prefetches",
+},
+{
+	.name = "PM_IOPS_CMPL",
+	.code = 0x10014,
+	.short_desc = "Internal Operations completed",
+	.long_desc = "Number of internal operations that completed.",
+},
+{
+	.name = "PM_L2_SYS_PUMP",
+	.code = 0x36482,
+	.short_desc = "RC req that was a global (aka system) pump attempt",
+	.long_desc = "RC req that was a global (aka system) pump attempt",
+},
+{
+	.name = "PM_L2_RCLD_BUSY_RC_FULL",
+	.code = 0x46282,
+	.short_desc = " L2  activated Busy to the core for loads due to all RC full",
+	.long_desc = " L2  activated Busy to the core for loads due to all RC full",
+},
+{
+	.name = "PM_LSU_LMQ_S0_ALLOC",
+	.code = 0xd0a1,
+	.short_desc = "Slot 0 of LMQ valid",
+	.long_desc = "Slot 0 of LMQ valid",
+},
+{
+	.name = "PM_FLUSH_DISP_SYNC",
+	.code = 0x2088,
+	.short_desc = "Dispatch Flush: Sync",
+	.long_desc = "Dispatch Flush: Sync",
+},
+{
+	.name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
+	.code = 0x4002a,
+	.short_desc = "Marked ld latency Data source 1011  (L2.75/L3.75 M different 4 chip node)",
+	.long_desc = "Marked ld latency Data source 1011  (L2.75/L3.75 M different 4 chip node)",
+},
+{
+	.name = "PM_L2_IC_INV",
+	.code = 0x26180,
+	.short_desc = "Icache Invalidates from L2 ",
+	.long_desc = "Icache Invalidates from L2 ",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L21_MOD_CYC",
+	.code = 0x40024,
+	.short_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)",
+	.long_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)",
+},
+{
+	.name = "PM_L3_PREF_LDST",
+	.code = 0xd8ac,
+	.short_desc = "L3 cache prefetches LD + ST",
+	.long_desc = "L3 cache prefetches LD + ST",
+},
+{
+	.name = "PM_LSU_SRQ_EMPTY_CYC",
+	.code = 0x40008,
+	.short_desc = "ALL threads srq empty",
+	.long_desc = "The Store Request Queue is empty",
+},
+{
+	.name = "PM_LSU_LMQ_S0_VALID",
+	.code = 0xd0a0,
+	.short_desc = "Slot 0 of LMQ valid",
+	.long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the LRQ is split between the two threads (16 entries each).",
+},
+{
+	.name = "PM_FLUSH_PARTIAL",
+	.code = 0x2086,
+	.short_desc = "Partial flush",
+	.long_desc = "Partial flush",
+},
+{
+	.name = "PM_VSU1_FMA_DOUBLE",
+	.code = 0xa092,
+	.short_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)",
+	.long_desc = "four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)",
+},
+{
+	.name = "PM_1PLUS_PPC_DISP",
+	.code = 0x400f2,
+	.short_desc = "Cycles at least one Instr Dispatched",
+	.long_desc = "A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.",
+},
+{
+	.name = "PM_DATA_FROM_L2MISS",
+	.code = 0x200fe,
+	.short_desc = "Demand LD - L2 Miss (not L2 hit)",
+	.long_desc = "The processor's Data Cache was reloaded but not from the local L2.",
+},
+{
+	.name = "PM_SUSPENDED",
+	.code = 0x0,
+	.short_desc = "Counter OFF",
+	.long_desc = "The counter is suspended (does not count)",
+},
+{
+	.name = "PM_VSU0_FMA",
+	.code = 0xa084,
+	.short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!",
+	.long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!",
+},
+{
+	.name = "PM_CMPLU_STALL_SCALAR",
+	.code = 0x40012,
+	.short_desc = "Completion stall caused by FPU instruction",
+	.long_desc = "Completion stall caused by FPU instruction",
+},
+{
+	.name = "PM_STCX_FAIL",
+	.code = 0xc09a,
+	.short_desc = "STCX failed",
+	.long_desc = "A stcx (stwcx or stdcx) failed",
+},
+{
+	.name = "PM_VSU0_FSQRT_FDIV_DOUBLE",
+	.code = 0xa094,
+	.short_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ",
+	.long_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ",
+},
+{
+	.name = "PM_DC_PREF_DST",
+	.code = 0xd0b0,
+	.short_desc = "Data Stream Touch",
+	.long_desc = "A prefetch stream was started using the DST instruction.",
+},
+{
+	.name = "PM_VSU1_SCAL_SINGLE_ISSUED",
+	.code = 0xb086,
+	.short_desc = "Single Precision scalar instruction issued on Pipe1",
+	.long_desc = "Single Precision scalar instruction issued on Pipe1",
+},
+{
+	.name = "PM_L3_HIT",
+	.code = 0x1f080,
+	.short_desc = "L3 Hits",
+	.long_desc = "L3 Hits",
+},
+{
+	.name = "PM_L2_GLOB_GUESS_WRONG",
+	.code = 0x26482,
+	.short_desc = "L2 guess glb and guess was not correct (ie data local)",
+	.long_desc = "L2 guess glb and guess was not correct (ie data local)",
+},
+{
+	.name = "PM_MRK_DFU_FIN",
+	.code = 0x20032,
+	.short_desc = "Decimal Unit marked Instruction Finish",
+	.long_desc = "The Decimal Floating Point Unit finished a marked instruction.",
+},
+{
+	.name = "PM_INST_FROM_L1",
+	.code = 0x4080,
+	.short_desc = "Instruction fetches from L1",
+	.long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_BRU_FIN",
+	.code = 0x10068,
+	.short_desc = "Branch Instruction Finished ",
+	.long_desc = "The Branch execution unit finished an instruction",
+},
+{
+	.name = "PM_IC_DEMAND_REQ",
+	.code = 0x4088,
+	.short_desc = "Demand Instruction fetch request",
+	.long_desc = "Demand Instruction fetch request",
+},
+{
+	.name = "PM_VSU1_FSQRT_FDIV_DOUBLE",
+	.code = 0xa096,
+	.short_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ",
+	.long_desc = "eight flop DP vector operations (xvfdivdp, xvsqrtdp ",
+},
+{
+	.name = "PM_VSU1_FMA",
+	.code = 0xa086,
+	.short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!",
+	.long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!",
+},
+{
+	.name = "PM_MRK_LD_MISS_L1",
+	.code = 0x20036,
+	.short_desc = "Marked DL1 Demand Miss",
+	.long_desc = "Marked L1 D cache load misses",
+},
+{
+	.name = "PM_VSU0_2FLOP_DOUBLE",
+	.code = 0xa08c,
+	.short_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)  ",
+	.long_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)  ",
+},
+{
+	.name = "PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM",
+	.code = 0xd8bc,
+	.short_desc = "Dcache Strided prefetch stream confirmed (software + hardware)",
+	.long_desc = "Dcache Strided prefetch stream confirmed (software + hardware)",
+},
+{
+	.name = "PM_INST_PTEG_FROM_L31_SHR",
+	.code = 0x2e056,
+	.short_desc = "Instruction PTEG loaded from another L3 on same chip shared",
+	.long_desc = "Instruction PTEG loaded from another L3 on same chip shared",
+},
+{
+	.name = "PM_MRK_LSU_REJECT_ERAT_MISS",
+	.code = 0x30064,
+	.short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)",
+	.long_desc = "LSU marked reject due to ERAT (up to 2 per cycle)",
+},
+{
+	.name = "PM_MRK_DATA_FROM_L2MISS",
+	.code = 0x4d048,
+	.short_desc = "Marked data loaded missed L2",
+	.long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.",
+},
+{
+	.name = "PM_DATA_FROM_RL2L3_SHR",
+	.code = 0x1c04c,
+	.short_desc = "Data loaded from remote L2 or L3 shared",
+	.long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load",
+},
+{
+	.name = "PM_INST_FROM_PREF",
+	.code = 0x14046,
+	.short_desc = "Instruction fetched from prefetch",
+	.long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions",
+},
+{
+	.name = "PM_VSU1_SQ",
+	.code = 0xb09e,
+	.short_desc = "Store Vector Issued on Pipe1",
+	.long_desc = "Store Vector Issued on Pipe1",
+},
+{
+	.name = "PM_L2_LD_DISP",
+	.code = 0x36180,
+	.short_desc = "All successful load dispatches",
+	.long_desc = "All successful load dispatches",
+},
+{
+	.name = "PM_L2_DISP_ALL",
+	.code = 0x46080,
+	.short_desc = "All successful LD/ST dispatches for this thread(i+d)",
+	.long_desc = "All successful LD/ST dispatches for this thread(i+d)",
+},
+{
+	.name = "PM_THRD_GRP_CMPL_BOTH_CYC",
+	.code = 0x10012,
+	.short_desc = "Cycles group completed by both threads",
+	.long_desc = "Cycles that both threads completed.",
+},
+{
+	.name = "PM_VSU_FSQRT_FDIV_DOUBLE",
+	.code = 0xa894,
+	.short_desc = "DP vector versions of fdiv,fsqrt ",
+	.long_desc = "DP vector versions of fdiv,fsqrt ",
+},
+{
+	.name = "PM_BR_MPRED",
+	.code = 0x400f6,
+	.short_desc = "Number of Branch Mispredicts",
+	.long_desc = "A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both",
+},
+{
+	.name = "PM_INST_PTEG_FROM_DL2L3_SHR",
+	.code = 0x3e054,
+	.short_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+	.long_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+},
+{
+	.name = "PM_VSU_1FLOP",
+	.code = 0xa880,
+	.short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished",
+	.long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished",
+},
+{
+	.name = "PM_HV_CYC",
+	.code = 0x2000a,
+	.short_desc = "cycles in hypervisor mode ",
+	.long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)",
+},
+{
+	.name = "PM_MRK_DATA_FROM_RL2L3_SHR",
+	.code = 0x1d04c,
+	.short_desc = "Marked data loaded from remote L2 or L3 shared",
+	.long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load",
+},
+{
+	.name = "PM_DTLB_MISS_16M",
+	.code = 0x4c05e,
+	.short_desc = "Data TLB miss for 16M page",
+	.long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+	.name = "PM_MRK_LSU_FIN",
+	.code = 0x40032,
+	.short_desc = "Marked LSU instruction finished",
+	.long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
+},
+{
+	.name = "PM_LSU1_LMQ_LHR_MERGE",
+	.code = 0xd09a,
+	.short_desc = "LS1 Load Merge with another cacheline request",
+	.long_desc = "LS1 Load Merge with another cacheline request",
+},
+{
+	.name = "PM_IFU_FIN",
+	.code = 0x40066,
+	.short_desc = "IFU Finished a (non-branch) instruction",
+	.long_desc = "The Instruction Fetch Unit finished an instruction",
+},
+{
+	.name = "PM_1THRD_CON_RUN_INSTR",
+	.code = 0x30062,
+	.short_desc = "1 thread Concurrent Run Instructions",
+	.long_desc = "1 thread Concurrent Run Instructions",
+},
+{
+	.name = "PM_CMPLU_STALL_COUNT",
+	.code = 0x4000B,
+	.short_desc = "Marked LSU instruction finished",
+	.long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete",
+},
+{
+	.name = "PM_MEM0_PB_RD_CL",
+	.code = 0x30083,
+	.short_desc = "Nest events (MC0/MC1/PB/GX), Pair2 Bit1",
+	.long_desc = "Nest events (MC0/MC1/PB/GX), Pair2 Bit1",
+},
+{
+	.name = "PM_THRD_1_RUN_CYC",
+	.code = 0x10060,
+	.short_desc = "1 thread in Run Cycles",
+	.long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work.  The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.",
+},
+{
+	.name = "PM_THRD_2_CONC_RUN_INSTR",
+	.code = 0x40062,
+	.short_desc = "2 thread Concurrent Run Instructions",
+	.long_desc = "2 thread Concurrent Run Instructions",
+},
+{
+	.name = "PM_THRD_2_RUN_CYC",
+	.code = 0x20060,
+	.short_desc = "2 thread in Run Cycles",
+	.long_desc = "2 thread in Run Cycles",
+},
+{
+	.name = "PM_THRD_3_CONC_RUN_INST",
+	.code = 0x10062,
+	.short_desc = "3 thread in Run Cycles",
+	.long_desc = "3 thread in Run Cycles",
+},
+{
+	.name = "PM_THRD_3_RUN_CYC",
+	.code = 0x30060,
+	.short_desc = "3 thread in Run Cycles",
+	.long_desc = "3 thread in Run Cycles",
+},
+{
+	.name = "PM_THRD_4_CONC_RUN_INST",
+	.code = 0x20062,
+	.short_desc = "4 thread in Run Cycles",
+	.long_desc = "4 thread in Run Cycles",
+},
+{
+	.name = "PM_THRD_4_RUN_CYC",
+	.code = 0x40060,
+	.short_desc = "4 thread in Run Cycles",
+	.long_desc = "4 thread in Run Cycles",
+},
+/* Terminating entry required */
+{
+	.name = NULL,
+	.code = 0,
+	.short_desc = NULL,
+	.long_desc = NULL,
+}
+};
+#endif
+
