From patchwork Thu Mar 26 09:14:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ying.zhang@freescale.com X-Patchwork-Id: 454977 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E2415140142 for ; Thu, 26 Mar 2015 22:58:12 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id AACF81A0CAE for ; Thu, 26 Mar 2015 22:58:12 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org X-Greylist: delayed 5464 seconds by postgrey-1.35 at bilbo; Thu, 26 Mar 2015 22:39:31 AEDT Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bbn0104.outbound.protection.outlook.com [157.56.111.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 20CC11A0144 for ; Thu, 26 Mar 2015 22:39:30 +1100 (AEDT) Received: from DM2PR0301MB1309.namprd03.prod.outlook.com (25.160.222.154) by DM2PR0301MB0783.namprd03.prod.outlook.com (25.160.97.154) with Microsoft SMTP Server (TLS) id 15.1.112.19; Thu, 26 Mar 2015 10:06:20 +0000 Received: from BN3PR0301CA0069.namprd03.prod.outlook.com (25.160.152.165) by DM2PR0301MB1309.namprd03.prod.outlook.com (25.160.222.154) with Microsoft SMTP Server (TLS) id 15.1.125.19; Thu, 26 Mar 2015 10:06:17 +0000 Received: from BN1AFFO11FD025.protection.gbl (2a01:111:f400:7c10::185) by BN3PR0301CA0069.outlook.office365.com (2a01:111:e400:401e::37) with Microsoft SMTP Server (TLS) id 15.1.125.19 via Frontend Transport; Thu, 26 Mar 2015 10:06:16 +0000 Received: from tx30smr01.am.freescale.net ([192.88.168.50]) by BN1AFFO11FD025.mail.protection.outlook.com ([10.58.52.85]) with Microsoft SMTP Server (TLS) id 15.1.130.10 via Frontend Transport; Thu, 26 Mar 2015 10:06:16 +0000 Received: from Tank.ap.freescale.net (tank.ap.freescale.net [10.193.20.104]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t2QA6D7C029805; Thu, 26 Mar 2015 03:06:14 -0700 From: To: , Subject: [PATCH 1/3] powerpc/dts: Add TDM device tree nodes for P1021RDB Date: Thu, 26 Mar 2015 17:14:14 +0800 Message-ID: <1427361254-4639-1-git-send-email-ying.zhang@freescale.com> X-Mailer: git-send-email 1.8.4.1 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=ying.zhang@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(279900001)(339900001)(199003)(189002)(92566002)(36756003)(50466002)(33646002)(47776003)(229853001)(106466001)(77156002)(15975445007)(77096005)(50226001)(48376002)(87936001)(450100001)(105606002)(86362001)(575784001)(62966003)(19625305001)(50986999)(19580405001)(19580395003)(86152002)(46102003)(85426001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB1309; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB1309; UriScan:; BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB0783; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:DM2PR0301MB1309; BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB1309; X-Forefront-PRVS: 0527DFA348 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2015 10:06:16.7039 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB1309 X-OriginatorOrg: freescale.com X-Mailman-Approved-At: Thu, 26 Mar 2015 22:54:41 +1100 Cc: Xie Xiaobo , Ying Zhang X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Ying Zhang The dts file support QE-TDM function and PQ-MDS-T1 card for P1021RDB. PQ-MDS-T1 is connected to the board by PMC, there is a zarlink le88266 on the card, we configure it by QE-SPI. Because PMC has a shared CS pin with L2switch, so we do the device tree fixup in uboot. Change-Id: I7ecee0d93a105ef158455238fb003a2ad2ca32e7 Signed-off-by: Ying Zhang Signed-off-by: Xie Xiaobo Reviewed-on: http://git.am.freescale.net:8181/900 Reviewed-by: Fleming Andrew-AFLEMING Tested-by: Fleming Andrew-AFLEMING --- arch/powerpc/boot/dts/p1021rdb-pc_32b.dts | 191 +++++++++++++++++++++++++++++- 1 file changed, 187 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts index 7cefa12..0fdb78f 100644 --- a/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts +++ b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts @@ -48,10 +48,96 @@ ranges = <0x0 0x0 0x0 0xef000000 0x01000000 0x1 0x0 0x0 0xff800000 0x00040000 0x2 0x0 0x0 0xffb00000 0x00020000>; + + pq_mds_t1: tdmphy@2,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <2 0 0x10000>; + ranges = <0 2 0 0x10000>; + compatible = "fsl,pq-mds-t1"; + + dallas: ds26528@0 { + compatible = "dallas,ds26528"; + reg = <0 0x2000>; + line-rate = "e1"; + trans-mode = "normal"; + }; + + pld-reg@2000 { + compatible = "fsl,pq-mds-t1-pld"; + reg = <0x2000 0x1000>; + fsl,card-support = <&dallas>; + }; + }; }; soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; + + par_io@e0100 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe0100 0x60>; + ranges = <0x0 0xe0100 0x60>; + device_type = "par_io"; + num-ports = <3>; + + qe_pio_b: gpio-controller@20 { + #gpio-cells = <2>; + compatible = "fsl,mpc8569-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x20 0x18>; + gpio-controller; + }; + + pio_qe_spi: qe_spi_pin@01 { + pio-map = < + 0x1 0x13 0x1 0x0 0x3 0x0 /* QE_MUX_SPIMOSI */ + 0x1 0x15 0x1 0x0 0x3 0x0 /* QE_MUX_CLK*/ + 0x1 0x16 0x2 0x0 0x3 0x0 /* QE_MUX_SPIMISO*/ + 0x1 0x1d 0x1 0x0 0x0 0x0>; /* QE_SPISEL_MASTER*/ + }; + + pio_tdma: tdm_pin@01 { + pio-map = < + 0x1 0xc 0x2 0x0 0x1 0x0 /* CLK3 */ + 0x1 0xd 0x2 0x0 0x1 0x0 /* CLK4 */ + 0x1 0x18 0x3 0x0 0x1 0x0 /* TDMA_RXD0_OPT2*/ + 0x1 0x17 0x3 0x0 0x1 0x0 /* TDMA_TXD0_OPT2*/ + 0x1 0x1a 0x2 0x0 0x1 0x0 /* TDMA_RSYNC_OPT2*/ + 0x1 0x19 0x2 0x0 0x1 0x0>; /* TDMA_TSYNC_OPT2*/ + }; + + pio_tdmb: tdm_pin@02 { + pio-map = < + 0x1 0x1 0x2 0x0 0x1 0x0 /* CLK5 */ + 0x0 0x1b 0x2 0x0 0x1 0x0 /* CLK6 */ + 0x0 0x1d 0x3 0x0 0x1 0x0 /* TDMB_RXD0*/ + 0x1 0x0 0x3 0x0 0x1 0x0 /* TDMB_TXD0*/ + 0x0 0x1f 0x2 0x0 0x1 0x0 /* TDMB_RSYNC */ + 0x0 0x1e 0x2 0x0 0x1 0x0>; /* TDMB_TSYNC */ + }; + + pio_tdmc: tdm_pin@03 { + pio-map = < + 0x1 0xa 0x2 0x0 0x1 0x0 /* CLK7 */ + 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ + 0x1 0x5 0x3 0x0 0x1 0x0 /* TDMC_RXD0*/ + 0x1 0x4 0x3 0x0 0x1 0x0 /* TDMC_TXD0*/ + 0x1 0x7 0x2 0x0 0x1 0x0 /* TDMC_RSYNC */ + 0x1 0x6 0x2 0x0 0x1 0x0>; /* TDMC_TSYNC */ + }; + + pio_tdmd: tdm_pin@04 { + pio-map = < + 0x2 0x0 0x2 0x0 0x1 0x0 /* CLK14 */ + 0x1 0x1f 0x2 0x0 0x1 0x0 /* CLK15 */ + 0x0 0x13 0x3 0x0 0x1 0x0 /* TDMD_RXD0_OPT2*/ + 0x0 0x12 0x3 0x0 0x1 0x0 /* TDMD_TXD0_OPT2*/ + 0x0 0x15 0x2 0x0 0x1 0x0 /* TDMD_RSYNC_OPT2*/ + 0x0 0x14 0x2 0x0 0x1 0x0>; /* TDMD_TSYNC_OPT2*/ + }; + }; }; pci0: pcie@ffe09000 { @@ -85,10 +171,107 @@ }; qe: qe@ffe80000 { - ranges = <0x0 0x0 0xffe80000 0x40000>; - reg = <0 0xffe80000 0 0x480>; - brg-frequency = <0>; - bus-frequency = <0>; + ranges = <0x0 0x0 0xffe80000 0x40000>; + reg = <0 0xffe80000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + + spi@4c0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; + reg = <0x4c0 0x40>; + cell-index = <0>; + interrupts = <2>; + interrupt-parent = <&qeic>; + pio-handle = <&pio_qe_spi>; + gpios = <&qe_pio_b 29 0>; + mode = "cpu-qe"; + + legerity@0 { + compatible = "zarlink,le88266"; + reg = <0>; + spi-max-frequency = <8000000>; + }; + }; + + si1: si@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-siram"; + reg = <0x1000 0x800>; + }; + + tdma: ucc@2000 { + compatible = "fsl,ucc-tdm"; + rx-clock-name = "clk3"; + tx-clock-name = "clk4"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot = <0xfffffffe>; + fsl,rx-timeslot = <0xfffffffe>; + pio-handle = <&pio_tdma>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + phy-handle = <&pq_mds_t1>; + }; + + tdmb: ucc@2200 { + compatible = "fsl,ucc-tdm"; + rx-clock-name = "clk5"; + tx-clock-name = "clk6"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot = <0xfffffffe>; + fsl,rx-timeslot = <0xfffffffe>; + pio-handle = <&pio_tdmb>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <1>; + fsl,siram-entry-id = <2>; + phy-handle = <&pq_mds_t1>; + }; + + tdmc: ucc@2400 { + compatible = "fsl,ucc-tdm"; + rx-clock-name = "clk7"; + tx-clock-name = "clk13"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot = <0xfffffffe>; + fsl,rx-timeslot = <0xfffffffe>; + pio-handle = <&pio_tdmc>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <2>; + fsl,siram-entry-id = <4>; + phy-handle = <&pq_mds_t1>; + }; + + tdmd: ucc@2600 { + compatible = "fsl,ucc-tdm"; + rx-clock-name = "clk14"; + tx-clock-name = "clk15"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + pio-handle = <&pio_tdmd>; + fsl,tx-timeslot = <0xfffffffe>; + fsl,rx-timeslot = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <3>; + fsl,siram-entry-id = <6>; + phy-handle = <&pq_mds_t1>; + }; }; };