From patchwork Tue Mar 3 05:17:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 445551 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BB394140161 for ; Tue, 3 Mar 2015 16:46:25 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 8BD821A0851 for ; Tue, 3 Mar 2015 16:46:25 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 17F791A04D4 for ; Tue, 3 Mar 2015 16:43:31 +1100 (AEDT) Received: by ozlabs.org (Postfix) id E7EF3140161; Tue, 3 Mar 2015 16:43:30 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bn0109.outbound.protection.outlook.com [157.56.110.109]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 11943140146 for ; Tue, 3 Mar 2015 16:43:29 +1100 (AEDT) Received: from BN3PR0301CA0058.namprd03.prod.outlook.com (25.160.152.154) by CY1PR0301MB1273.namprd03.prod.outlook.com (25.161.214.21) with Microsoft SMTP Server (TLS) id 15.1.99.14; Tue, 3 Mar 2015 05:27:58 +0000 Received: from BL2FFO11FD016.protection.gbl (2a01:111:f400:7c09::186) by BN3PR0301CA0058.outlook.office365.com (2a01:111:e400:401e::26) with Microsoft SMTP Server (TLS) id 15.1.99.9 via Frontend Transport; Tue, 3 Mar 2015 05:27:57 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD016.mail.protection.outlook.com (10.173.160.224) with Microsoft SMTP Server (TLS) id 15.1.99.6 via Frontend Transport; Tue, 3 Mar 2015 05:27:57 +0000 Received: from kvm.ap.freescale.net (kvm.ap.freescale.net [10.232.14.24]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t235RrVU019197; Mon, 2 Mar 2015 22:27:54 -0700 From: Bharat Bhushan To: Subject: [PATCH 1/4 RFC] fsl/msi: have msiir register address absolute rather than offset Date: Tue, 3 Mar 2015 10:47:43 +0530 Message-ID: <1425359866-31049-1-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.9.3 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Bharat.Bhushan@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(92566002)(110136001)(46102003)(575784001)(86362001)(50986999)(47776003)(36756003)(50466002)(50226001)(48376002)(2351001)(19580395003)(19580405001)(106466001)(229853001)(87936001)(77156002)(85426001)(104016003)(6806004)(2371004)(450100001)(105606002)(62966003)(77096005); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB1273; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB1273; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006); SRVR:CY1PR0301MB1273; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1273; X-Forefront-PRVS: 0504F29D72 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2015 05:27:57.2714 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1273 Cc: Bharat Bhushan , linuxppc-dev@ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Having absolute address simplifies the code and also removes the confusion around feature->msiir_offset and msi_data->msiir_offset. Signed-off-by: Bharat Bhushan --- arch/powerpc/sysdev/fsl_msi.c | 9 +++------ arch/powerpc/sysdev/fsl_msi.h | 2 +- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 4bbb4b8..ec3161b 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -157,7 +157,7 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, if (reg && (len == sizeof(u64))) address = be64_to_cpup(reg); else - address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset; + address = msi_data->msiir; msg->address_lo = lower_32_bits(address); msg->address_hi = upper_32_bits(address); @@ -430,18 +430,15 @@ static int fsl_of_msi_probe(struct platform_device *dev) dev->dev.of_node->full_name); goto error_out; } - msi->msiir_offset = - features->msiir_offset + (res.start & 0xfffff); /* * First read the MSIIR/MSIIR1 offset from dts * On failure use the hardcode MSIIR offset */ if (of_address_to_resource(dev->dev.of_node, 1, &msiir)) - msi->msiir_offset = features->msiir_offset + - (res.start & MSIIR_OFFSET_MASK); + msi->msiir = res.start + features->msiir_offset; else - msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK; + msi->msiir = msiir.start; } msi->feature = features->fsl_pic_ip; diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h index 420cfcb..9b0ab84 100644 --- a/arch/powerpc/sysdev/fsl_msi.h +++ b/arch/powerpc/sysdev/fsl_msi.h @@ -34,7 +34,7 @@ struct fsl_msi { unsigned long cascade_irq; - u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */ + phys_addr_t msiir; /* MSIIR Address in CCSR */ u32 ibs_shift; /* Shift of interrupt bit select */ u32 srs_shift; /* Shift of the shared interrupt register select */ void __iomem *msi_regs;