From patchwork Wed Jan 14 07:08:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 428803 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8F46214027C for ; Wed, 14 Jan 2015 18:14:56 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 7E1E11A15C5 for ; Wed, 14 Jan 2015 18:14:56 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id B75F71A0C8D for ; Wed, 14 Jan 2015 18:09:40 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 5ACA414029C; Wed, 14 Jan 2015 18:09:40 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EA91C14029D for ; Wed, 14 Jan 2015 18:09:39 +1100 (AEDT) Received: from /spool/local by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 14 Jan 2015 17:09:38 +1000 Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 6E18D2CE8047 for ; Wed, 14 Jan 2015 18:09:37 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t0E79bIH15859864 for ; Wed, 14 Jan 2015 18:09:37 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t0E79Yis006315 for ; Wed, 14 Jan 2015 18:09:36 +1100 Received: from polynomials.in.ibm.com (polynomials.in.ibm.com [9.124.31.148]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t0E78prg005057; Wed, 14 Jan 2015 18:09:30 +1100 From: Anshuman Khandual To: linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org Subject: [PATCH V7 6/8] powerpc, ptrace: Enable support for miscellaneous debug registers Date: Wed, 14 Jan 2015 12:38:48 +0530 Message-Id: <1421219330-19984-7-git-send-email-khandual@linux.vnet.ibm.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1421219330-19984-1-git-send-email-khandual@linux.vnet.ibm.com> References: <1421219330-19984-1-git-send-email-khandual@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15011407-0025-0000-0000-000000E9D6CB Cc: shuahkh@osg.samsung.com, mikey@neuling.org, james.hogan@imgtec.com, avagin@openvz.org, Paul.Clothier@imgtec.com, peterz@infradead.org, palves@redhat.com, oleg@redhat.com, davem@davemloft.net, dhowells@redhat.com, kirjanov@gmail.com, davej@redhat.com, akpm@linux-foundation.org, sukadev@linux.vnet.ibm.com, tglx@linutronix.de, sam.bobroff@au1.ibm.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This patch enables get and set of miscellaneous debug registers through ptrace PTRACE_GETREGSET-PTRACE_SETREGSET interface by implementing new powerpc specific register set REGSET_MISC support corresponding to the new ELF core note NT_PPC_MISC added previously in this regard. Signed-off-by: Anshuman Khandual --- arch/powerpc/include/uapi/asm/elf.h | 1 + arch/powerpc/kernel/ptrace.c | 133 ++++++++++++++++++++++++++++++++++++ 2 files changed, 134 insertions(+) diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h index fdc8e2f..a41bd98 100644 --- a/arch/powerpc/include/uapi/asm/elf.h +++ b/arch/powerpc/include/uapi/asm/elf.h @@ -93,6 +93,7 @@ #define ELF_NFPREG 33 /* includes fpscr */ #define ELF_NVMX 34 /* includes all vector registers */ #define ELF_NTMSPRREG 7 /* includes TM sprs, org_msr, dscr, tar, ppr */ +#define ELF_NMISCREG 3 /* includes dscr, tar, ppr */ typedef unsigned long elf_greg_t64; typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG]; diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index b14397c..38a1147 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1371,6 +1371,122 @@ static int tm_cvmx_set(struct task_struct *target, } #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ +#ifdef CONFIG_PPC64 +/** + * get_misc_dbg() - get MISC debug registers + * @target: The target task. + * @regset: The user regset structure. + * @pos: The buffer position. + * @count: Number of bytes to copy. + * @kbuf: Kernel buffer to copy from. + * @ubuf: User buffer to copy into. + * + * This function gets various miscellaneous debug registers which includes + * DSCR, PPR and TAR. The userspace intarface buffer layout is as follows. + * + * struct { + * unsigned long dscr; + * unsigned long ppr; + * unsigned long tar; + * }; + * + * The data element 'tar' in the structure will be valid only if the kernel + * has CONFIG_PPC_BOOK3S_64 config option enabled. + */ +static int get_misc_dbg(struct task_struct *target, + const struct user_regset *regset, unsigned int pos, + unsigned int count, void *kbuf, void __user *ubuf) +{ + int ret; + + /* Build test */ + BUILD_BUG_ON(TSO(dscr) + 2 * sizeof(unsigned long) != TSO(ppr)); + +#ifdef CONFIG_PPC_BOOK3S_64 + BUILD_BUG_ON(TSO(ppr) + sizeof(unsigned long) != TSO(tar)); +#endif + + /* DSCR register */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.dscr, 0, + sizeof(unsigned long)); + + /* PPR register */ + if (!ret) + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.ppr, + sizeof(unsigned long), + 2 * sizeof(unsigned long)); + +#ifdef CONFIG_PPC_BOOK3S_64 + /* TAR register */ + if (!ret) + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.tar, + 2 * sizeof(unsigned long), + 3 * sizeof(unsigned long)); +#endif + return ret; +} + +/** + * set_misc_dbg() - set MISC debug registers + * @target: The target task. + * @regset: The user regset structure. + * @pos: The buffer position. + * @count: Number of bytes to copy. + * @kbuf: Kernel buffer to copy into. + * @ubuf: User buffer to copy from. + * + * This function sets various miscellaneous debug registers which includes + * DSCR, PPR and TAR. The userspace intarface buffer layout is as follows. + * + * struct { + * unsigned long dscr; + * unsigned long ppr; + * unsigned long tar; + * }; + * + * The data element 'tar' in the structure will be valid only if the kernel + * has CONFIG_PPC_BOOK3S_64 config option enabled. + */ +static int set_misc_dbg(struct task_struct *target, + const struct user_regset *regset, unsigned int pos, + unsigned int count, const void *kbuf, + const void __user *ubuf) +{ + int ret; + + /* Build test */ + BUILD_BUG_ON(TSO(dscr) + 2 * sizeof(unsigned long) != TSO(ppr)); + +#ifdef CONFIG_PPC_BOOK3S_64 + BUILD_BUG_ON(TSO(ppr) + sizeof(unsigned long) != TSO(tar)); +#endif + + /* DSCR register */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.dscr, 0, + sizeof(unsigned long)); + + /* PPR register */ + if (!ret) + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.ppr, + sizeof(unsigned long), + 2 * sizeof(unsigned long)); +#ifdef CONFIG_PPC_BOOK3S_64 + /* TAR register */ + if (!ret) + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.tar, + 2 * sizeof(unsigned long), + 3 * sizeof(unsigned long)); +#endif + return ret; +} +#endif /* CONFIG_PPC64 */ + /* * These are our native regset flavors. */ @@ -1392,6 +1508,9 @@ enum powerpc_regset { REGSET_TM_CFPR, /* TM checkpointed FPR registers */ REGSET_TM_CVMX, /* TM checkpointed VMX registers */ #endif +#ifdef CONFIG_PPC64 + REGSET_MISC /* Miscellaneous debug registers */ +#endif }; static const struct user_regset native_regsets[] = { @@ -1448,6 +1567,13 @@ static const struct user_regset native_regsets[] = { .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set }, #endif +#ifdef CONFIG_PPC64 + [REGSET_MISC] = { + .core_note_type = NT_PPC_MISC, .n = ELF_NMISCREG, + .size = sizeof(u64), .align = sizeof(u64), + .get = get_misc_dbg, .set = set_misc_dbg + }, +#endif }; static const struct user_regset_view user_ppc_native_view = { @@ -1694,6 +1820,13 @@ static const struct user_regset compat_regsets[] = { .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set }, #endif +#ifdef CONFIG_PPC64 + [REGSET_MISC] = { + .core_note_type = NT_PPC_MISC, .n = ELF_NMISCREG, + .size = sizeof(u64), .align = sizeof(u64), + .get = get_misc_dbg, .set = set_misc_dbg + }, +#endif }; static const struct user_regset_view user_ppc_compat_view = {