From patchwork Fri Jul 26 10:27:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongbo Zhang X-Patchwork-Id: 262115 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id F17DA2C0192 for ; Fri, 26 Jul 2013 20:28:45 +1000 (EST) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe006.messaging.microsoft.com [216.32.180.189]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 95B9C2C010B for ; Fri, 26 Jul 2013 20:27:42 +1000 (EST) Received: from mail6-co1-R.bigfish.com (10.243.78.235) by CO1EHSOBE003.bigfish.com (10.243.66.66) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Jul 2013 10:27:38 +0000 Received: from mail6-co1 (localhost [127.0.0.1]) by mail6-co1-R.bigfish.com (Postfix) with ESMTP id 70FF1A40123; Fri, 26 Jul 2013 10:27:38 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail6-co1 (localhost.localdomain [127.0.0.1]) by mail6-co1 (MessageSwitch) id 1374834456273890_23493; Fri, 26 Jul 2013 10:27:36 +0000 (UTC) Received: from CO1EHSMHS030.bigfish.com (unknown [10.243.78.232]) by mail6-co1.bigfish.com (Postfix) with ESMTP id 3E3CF480048; Fri, 26 Jul 2013 10:27:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS030.bigfish.com (10.243.66.40) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 26 Jul 2013 10:27:34 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.136.1; Fri, 26 Jul 2013 10:27:33 +0000 Received: from hongbo.ap.freescale.net (b45939-01.ap.freescale.net [10.193.20.52]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r6QARDSE022129; Fri, 26 Jul 2013 03:27:30 -0700 From: To: , , , , Subject: [PATCH v6 1/3] DMA: Freescale: revise device tree binding document Date: Fri, 26 Jul 2013 18:27:14 +0800 Message-ID: <1374834436-7149-2-git-send-email-hongbo.zhang@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374834436-7149-1-git-send-email-hongbo.zhang@freescale.com> References: <1374834436-7149-1-git-send-email-hongbo.zhang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Hongbo Zhang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Hongbo Zhang This patch updates the discription of each type of DMA controller and its channels, it is preparation for adding another new DMA controller binding, it also fixes some defects of indent for text alignment at the same time. Signed-off-by: Hongbo Zhang --- .../devicetree/bindings/powerpc/fsl/dma.txt | 52 +++++++++----------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index 2a4b4bc..ed703d9 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -1,33 +1,31 @@ -* Freescale 83xx DMA Controller +* Freescale DMA Controllers -Freescale PowerPC 83xx have on chip general purpose DMA controllers. +** Freescale Elo DMA Controller + This is a little-endian DMA controller, used in Freescale mpc83xx series + chips such as mpc8315, mpc8349, mpc8379 etc. Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma", where CHIP is the processor - (mpc8349, mpc8360, etc.) and the second is - "fsl,elo-dma" +- compatible : must include "fsl,elo-dma", and a "fsl,CHIP-dma" is + optional, where CHIP is the processor name. - reg : -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges : describes the mapping between the address space of the + DMA channels and the address space of the DMA controller. - cell-index : controller index. 0 for controller @ 0x8100 - interrupts : - interrupt-parent : optional, if needed for interrupt mapping - - DMA channel nodes: - - compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma-channel", where CHIP is the processor - (mpc8349, mpc8350, etc.) and the second is - "fsl,elo-dma-channel". However, see note below. + - compatible : must include "fsl,elo-dma-channel", and a + "fsl,CHIP-dma-channel" is optional, where CHIP is + the processor name, However, see note below. - reg : - cell-index : dma channel index starts at 0. Optional properties: - interrupts : - (on 83xx this is expected to be identical to - the interrupts property of the parent node) + (on 83xx this is expected to be identical to + the interrupts property of the parent node) - interrupt-parent : optional, if needed for interrupt mapping Example: @@ -70,27 +68,25 @@ Example: }; }; -* Freescale 85xx/86xx DMA Controller - -Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. +** Freescale EloPlus DMA Controller + This is DMA controller with extended addresses and chaining, mainly used in + Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as mpc8540, mpc8641 + p4080, bsc9131 etc. Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma", where CHIP is the processor - (mpc8540, mpc8540, etc.) and the second is - "fsl,eloplus-dma" +- compatible : must include "fsl,eloplus-dma", and a "fsl,CHIP-dma" is + optional, where CHIP is the processor name. - reg : - cell-index : controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges : describes the mapping between the address space of the + DMA channels and the address space of the DMA controller - DMA channel nodes: - - compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-dma-channel", where CHIP is the processor - (mpc8540, mpc8560, etc.) and the second is - "fsl,eloplus-dma-channel". However, see note below. + - compatible : must include "fsl,eloplus-dma-channel", and a + "fsl,CHIP-dma-channel" is optional, where CHIP is + the processor name, However, see note below. - cell-index : dma channel index starts at 0. - reg : - interrupts :