From patchwork Thu May 30 08:23:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 247473 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 505012C07D5 for ; Thu, 30 May 2013 18:27:16 +1000 (EST) Received: from e9.ny.us.ibm.com (e9.ny.us.ibm.com [32.97.182.139]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e9.ny.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 582342C008C for ; Thu, 30 May 2013 18:24:19 +1000 (EST) Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 30 May 2013 04:24:15 -0400 Received: from d01relay06.pok.ibm.com (d01relay06.pok.ibm.com [9.56.227.116]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 2942FC90042 for ; Thu, 30 May 2013 04:24:14 -0400 (EDT) Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay06.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r4U8OEVM36634786 for ; Thu, 30 May 2013 04:24:14 -0400 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r4U8OEIg026446 for ; Thu, 30 May 2013 04:24:14 -0400 Received: from shangw (shangw.cn.ibm.com [9.125.213.109]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id r4U8OBML026331; Thu, 30 May 2013 04:24:12 -0400 Received: by shangw (Postfix, from userid 1000) id 8AB20303D97; Thu, 30 May 2013 16:24:10 +0800 (CST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 05/23] powerpc/eeh: Trace PCI bus from PE Date: Thu, 30 May 2013 16:23:47 +0800 Message-Id: <1369902245-5886-6-git-send-email-shangw@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1369902245-5886-1-git-send-email-shangw@linux.vnet.ibm.com> References: <1369902245-5886-1-git-send-email-shangw@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13053008-7182-0000-0000-000007035D32 Cc: Gavin Shan X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" There're several types of PEs can be supported for now: PHB, Bus and Device dependent PE. For PCI bus dependent PE, tracing the corresponding PCI bus from PE (struct eeh_pe) would make the code more efficient. The patch also enables the retrieval of PCI bus based on the PCI device dependent PE. Signed-off-by: Gavin Shan --- arch/powerpc/include/asm/eeh.h | 1 + arch/powerpc/platforms/pseries/eeh_pe.c | 25 ++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h index 9230aa4..557d82a 100644 --- a/arch/powerpc/include/asm/eeh.h +++ b/arch/powerpc/include/asm/eeh.h @@ -62,6 +62,7 @@ struct eeh_pe { int check_count; /* Times of ignored error */ int freeze_count; /* Times of froze up */ int false_positives; /* Times of reported #ff's */ + struct pci_bus *bus; /* Top PCI bus for bus PE */ struct eeh_pe *parent; /* Parent PE */ struct list_head child_list; /* Link PE to the child list */ struct list_head edevs; /* Link list of EEH devices */ diff --git a/arch/powerpc/platforms/pseries/eeh_pe.c b/arch/powerpc/platforms/pseries/eeh_pe.c index 93ed9cb..03f8223 100644 --- a/arch/powerpc/platforms/pseries/eeh_pe.c +++ b/arch/powerpc/platforms/pseries/eeh_pe.c @@ -304,6 +304,7 @@ static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev) int eeh_add_to_parent_pe(struct eeh_dev *edev) { struct eeh_pe *pe, *parent; + struct eeh_dev *first_edev; eeh_lock(); @@ -326,6 +327,21 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev) pe->type = EEH_PE_BUS; edev->pe = pe; + /* + * For PCI bus sensitive PE, we can reset the parent + * bridge in order for hot-reset. However, the PCI + * devices including the associated EEH devices might + * be removed when EEH core is doing recovery. So that + * won't safe to retrieve the bridge through downstream + * EEH device. We have to trace the parent PCI bus, then + * the parent bridge explicitly. + */ + if (eeh_probe_mode_dev() && !pe->bus) { + first_edev = list_first_entry(&pe->edevs, + struct eeh_dev, list); + pe->bus = eeh_dev_to_pci_dev(first_edev)->bus; + } + /* Put the edev to PE */ list_add_tail(&edev->list, &pe->edevs); eeh_unlock(); @@ -639,13 +655,20 @@ struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe) if (pe->type & EEH_PE_PHB) { bus = pe->phb->bus; - } else if (pe->type & EEH_PE_BUS) { + } else if (pe->type & EEH_PE_BUS || + pe->type & EEH_PE_DEVICE) { + if (pe->bus) { + bus = pe->bus; + goto out; + } + edev = list_first_entry(&pe->edevs, struct eeh_dev, list); pdev = eeh_dev_to_pci_dev(edev); if (pdev) bus = pdev->bus; } +out: eeh_unlock(); return bus;