Message ID | 1346664130-7896-2-git-send-email-tie-fei.zang@freescale.com (mailing list archive) |
---|---|
State | Accepted, archived |
Commit | 9e67886becd7fab36c97ef43bb81515c18a66be1 |
Delegated to: | Kumar Gala |
Headers | show |
On Sep 3, 2012, at 4:22 AM, Roy Zang wrote: > Freescale PCIe IP block revision bigger than rev2.2 will also need > redefine the sequence of inbound windows. So change to use IP block > revision instead of compatible for the judgment. > > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> > --- > > arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++------ > 1 files changed, 8 insertions(+), 6 deletions(-) applied to next - k
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index a7b2a60..bce48e6 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -143,18 +143,20 @@ static void __init setup_pci_atmu(struct pci_controller *hose, pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", (u64)rsrc->start, (u64)resource_size(rsrc)); - if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { - win_idx = 2; - start_idx = 0; - end_idx = 3; - } - pci = ioremap(rsrc->start, resource_size(rsrc)); if (!pci) { dev_err(hose->parent, "Unable to map ATMU registers\n"); return; } + if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { + if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { + win_idx = 2; + start_idx = 0; + end_idx = 3; + } + } + /* Disable all windows (except powar0 since it's ignored) */ for(i = 1; i < 5; i++) out_be32(&pci->pow[i].powar, 0);
Freescale PCIe IP block revision bigger than rev2.2 will also need redefine the sequence of inbound windows. So change to use IP block revision instead of compatible for the judgment. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> --- arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-)