From patchwork Wed Jul 11 09:01:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Liu X-Patchwork-Id: 170398 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 210D42C046A for ; Wed, 11 Jul 2012 19:23:13 +1000 (EST) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe004.messaging.microsoft.com [216.32.180.14]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 8619D2C0211 for ; Wed, 11 Jul 2012 19:22:48 +1000 (EST) Received: from mail79-va3-R.bigfish.com (10.7.14.251) by VA3EHSOBE012.bigfish.com (10.7.40.62) with Microsoft SMTP Server id 14.1.225.23; Wed, 11 Jul 2012 09:20:22 +0000 Received: from mail79-va3 (localhost [127.0.0.1]) by mail79-va3-R.bigfish.com (Postfix) with ESMTP id A23D1E02D3; Wed, 11 Jul 2012 09:20:22 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839hd24he5bhf0ah107ah) Received: from mail79-va3 (localhost.localdomain [127.0.0.1]) by mail79-va3 (MessageSwitch) id 1341998420101216_29265; Wed, 11 Jul 2012 09:20:20 +0000 (UTC) Received: from VA3EHSMHS010.bigfish.com (unknown [10.7.14.246]) by mail79-va3.bigfish.com (Postfix) with ESMTP id 0A8EC6018C; Wed, 11 Jul 2012 09:20:20 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS010.bigfish.com (10.7.99.20) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 11 Jul 2012 09:20:17 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Wed, 11 Jul 2012 04:22:38 -0500 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6B9MakP020232; Wed, 11 Jul 2012 02:22:37 -0700 From: Qiang Liu To: , Subject: [PATCH v2 3/4] fsl-dma: change the release process of dma descriptor Date: Wed, 11 Jul 2012 17:01:25 +0800 Message-ID: <1341997285-18459-1-git-send-email-qiang.liu@freescale.com> X-Mailer: git-send-email 1.7.5.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Vinod Koul , Qiang Liu , herbert@gondor.hengli.com.au, Dan Williams , davem@davemloft.net X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Modify the release process of dma descriptor for avoiding exception when enable config NET_DMA, release dma descriptor from 1st to last second, the last descriptor which is reserved in current descriptor register may not be completed, race condition will be raised if free current descriptor. A race condition which is raised when use both of talitos and dmaengine to offload xor is because napi scheduler (NET_DMA is enabled) will sync all pending requests in dma channels, it affects the process of raid operations. The descriptor is freed which is submitted just now, but async_tx must check whether this depend tx descriptor is acked, there are poison contents in the invalid address, then BUG_ON() is thrown, so this descriptor will be freed in the next time. Cc: Dan Williams Cc: Vinod Koul Cc: Li Yang Signed-off-by: Qiang Liu --- drivers/dma/fsldma.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-) -- 1.7.5.1 diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 4f2f212..0ba3e40 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1035,14 +1035,22 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) static void dma_do_tasklet(unsigned long data) { struct fsldma_chan *chan = (struct fsldma_chan *)data; - struct fsl_desc_sw *desc, *_desc; + struct fsl_desc_sw *desc, *_desc, *prev = NULL; LIST_HEAD(ld_cleanup); unsigned long flags; + dma_addr_t curr_phys = get_cdar(chan); chan_dbg(chan, "tasklet entry\n"); spin_lock_irqsave(&chan->desc_lock, flags); + /* find the descriptor which is already completed */ + list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { + if (prev && desc->async_tx.phys == curr_phys) + break; + prev = desc; + } + /* update the cookie if we have some descriptors to cleanup */ if (!list_empty(&chan->ld_running)) { dma_cookie_t cookie; @@ -1058,13 +1066,14 @@ static void dma_do_tasklet(unsigned long data) * move the descriptors to a temporary list so we can drop the lock * during the entire cleanup operation */ - list_splice_tail_init(&chan->ld_running, &ld_cleanup); + list_cut_position(&ld_cleanup, &chan->ld_running, &prev->node); /* the hardware is now idle and ready for more */ chan->idle = true; /* - * Start any pending transactions automatically + * Start any pending transactions automatically if current descriptor + * list is completed * * In the ideal case, we keep the DMA controller busy while we go * ahead and free the descriptors below.