From patchwork Thu Jul 21 10:29:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shaohui xie X-Patchwork-Id: 106033 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id E86E5B7270 for ; Thu, 21 Jul 2011 21:29:10 +1000 (EST) Received: from TX2EHSOBE008.bigfish.com (tx2ehsobe004.messaging.microsoft.com [65.55.88.14]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 35559B6F85 for ; Thu, 21 Jul 2011 21:28:59 +1000 (EST) Received: from mail125-tx2-R.bigfish.com (10.9.14.247) by TX2EHSOBE008.bigfish.com (10.9.40.28) with Microsoft SMTP Server id 14.1.225.22; Thu, 21 Jul 2011 11:28:49 +0000 Received: from mail125-tx2 (localhost.localdomain [127.0.0.1]) by mail125-tx2-R.bigfish.com (Postfix) with ESMTP id D87EA8481F1; Thu, 21 Jul 2011 11:28:48 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh2a8h668h839h65h) X-Spam-TCS-SCL: 4:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail125-tx2 (localhost.localdomain [127.0.0.1]) by mail125-tx2 (MessageSwitch) id 1311247684606186_27442; Thu, 21 Jul 2011 11:28:04 +0000 (UTC) Received: from TX2EHSMHS039.bigfish.com (unknown [10.9.14.244]) by mail125-tx2.bigfish.com (Postfix) with ESMTP id 3D68113D81AA; Thu, 21 Jul 2011 11:27:08 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS039.bigfish.com (10.9.99.139) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 21 Jul 2011 11:27:05 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Thu, 21 Jul 2011 06:27:05 -0500 Received: from localhost.localdomain (rock.ap.freescale.net [10.193.20.106]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p6LBR2hD004620; Thu, 21 Jul 2011 06:27:03 -0500 (CDT) From: Shaohui Xie To: Subject: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error management registers Date: Thu, 21 Jul 2011 18:29:55 +0800 Message-ID: <1311244195-4418-1-git-send-email-Shaohui.Xie@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: kumar.gala@freescale.com, "Kai.Jiang" , Shaohui Xie X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org From: Kai.Jiang There are some differences of register offset and definition between pci and pcie error management registers. While, some other pci/pcie error management registers are nearly the same. Signed-off-by: Kai.Jiang Signed-off-by: Kumar Gala Signed-off-by: Shaohui Xie --- arch/powerpc/sysdev/fsl_pci.h | 31 +++++++++++++++++++++++++------ 1 files changed, 25 insertions(+), 6 deletions(-) difg --gite a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index a39ed5c..60a76e9 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -74,13 +74,32 @@ struct ccsr_pci { */ struct pci_inbound_window_regs piw[4]; +/* Merge PCI/PCI Express error management registers */ __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ - u8 res21[4]; - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ - u8 res22[4]; - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ - u8 res23[12]; - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ + __be32 pex_err_cap_dr; /* 0x.e04 */ + /* - PCI error capture disabled register */ + /* - PCIE has no this register */ + __be32 pex_err_en; /* 0x.e08 */ + /* - PCI/PCIE error interrupt enable register*/ + __be32 pex_err_attrib; /* 0x.e0c */ + /* - PCI error attributes capture register */ + /* - PCIE has no this register */ + __be32 pex_err_disr; /* 0x.e10 */ + /* - PCI error address capture register */ + /* - PCIE error disable register */ + __be32 pex_err_ext_addr; /* 0x.e14 */ + /* - PCI error extended addr capture register*/ + /* - PCIE has no this register */ + __be32 pex_err_dl; /* 0x.e18 */ + /* - PCI error data low capture register */ + /* - PCIE has no this register */ + __be32 pex_err_dh; /* 0x.e1c */ + /* - PCI error data high capture register */ + /* - PCIE has no this register */ + __be32 pex_err_cap_stat; /* 0x.e20 */ + /* - PCI gasket timer register */ + /* - PCIE error capture status register */ + u8 res24[4]; __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */