| Message ID | 1311244195-4418-1-git-send-email-Shaohui.Xie@freescale.com (mailing list archive) |
|---|---|
| State | Deferred |
| Delegated to: | Kumar Gala |
| Headers | show |
On Thu, Jul 21, 2011 at 5:29 AM, Shaohui Xie <Shaohui.Xie@freescale.com> wrote:
> + /* - PCIE has no this register */
I don't understand this sentence.
>From: Tabi Timur-B04825 >Sent: Thursday, July 21, 2011 11:59 PM >To: Xie Shaohui-B21989 >Cc: linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Jiang Kai-B18973 >Subject: Re: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error >management registers > >On Thu, Jul 21, 2011 at 5:29 AM, Shaohui Xie <Shaohui.Xie@freescale.com> >wrote: > >> + /* - PCIE has no this register >*/ > >I don't understand this sentence. > [Xie Shaohui] this patch intend to merge PCI and PCIe error management registers into a unit Structure, some register offsets where PCI has definitions while PCIe are reserved. For ex. On MPC8536, PCI has a register ERR_CAP_DR (PCI error capture disabled register) at offset 0xe04, But this offset is reserved in PCIe. Best Regards, Shaohui Xie
>-----Original Message----- >From: Xie Shaohui-B21989 >Sent: Thursday, July 21, 2011 6:30 PM >To: linuxppc-dev@lists.ozlabs.org >Cc: Gala Kumar-B11780; Jiang Kai-B18973; Kumar Gala; Xie Shaohui-B21989 >Subject: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error management >registers > >From: Kai.Jiang <Kai.Jiang@freescale.com> > >There are some differences of register offset and definition between pci >and pcie error management registers. While, some other pci/pcie error >management registers are nearly the same. > >Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> >Signed-off-by: Kumar Gala <galak@kernel.crashing.org> >Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> >--- > arch/powerpc/sysdev/fsl_pci.h | 31 +++++++++++++++++++++++++------ > 1 files changed, 25 insertions(+), 6 deletions(-) > >difg --gite a/arch/powerpc/sysdev/fsl_pci.h >b/arch/powerpc/sysdev/fsl_pci.h index a39ed5c..60a76e9 100644 >--- a/arch/powerpc/sysdev/fsl_pci.h >+++ b/arch/powerpc/sysdev/fsl_pci.h >@@ -74,13 +74,32 @@ struct ccsr_pci { > */ > struct pci_inbound_window_regs piw[4]; > >+/* Merge PCI/PCI Express error management registers */ > __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect >register */ >- u8 res21[4]; >- __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt >enable register */ >- u8 res22[4]; >- __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error >disable register */ >- u8 res23[12]; >- __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture >status register */ >+ __be32 pex_err_cap_dr; /* 0x.e04 */ >+ /* - PCI error capture disabled register */ >+ /* - PCIE has no this register */ >+ __be32 pex_err_en; /* 0x.e08 */ >+ /* - PCI/PCIE error interrupt enable >register*/ >+ __be32 pex_err_attrib; /* 0x.e0c */ >+ /* - PCI error attributes capture register >*/ >+ /* - PCIE has no this register */ >+ __be32 pex_err_disr; /* 0x.e10 */ >+ /* - PCI error address capture register */ >+ /* - PCIE error disable register */ >+ __be32 pex_err_ext_addr; /* 0x.e14 */ >+ /* - PCI error extended addr capture >register*/ >+ /* - PCIE has no this register */ >+ __be32 pex_err_dl; /* 0x.e18 */ >+ /* - PCI error data low capture register */ >+ /* - PCIE has no this register */ >+ __be32 pex_err_dh; /* 0x.e1c */ >+ /* - PCI error data high capture register */ >+ /* - PCIE has no this register */ >+ __be32 pex_err_cap_stat; /* 0x.e20 */ >+ /* - PCI gasket timer register */ >+ /* - PCIE error capture status register */ >+ > u8 res24[4]; > __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture >register 0 */ > __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture >register 0 */ >-- >1.6.4 [Xie Shaohui] I've verified this patch can apply for galak/powerpc.git 'next' branch with no change. Best Regards, Shaohui Xie
Hi all, Any concerns of this patch? Best Regards, Shaohui Xie >-----Original Message----- >From: Xie Shaohui-B21989 >Sent: Tuesday, July 26, 2011 2:50 PM >To: Kumar Gala >Cc: Jiang Kai-B18973; linuxppc-dev@lists.ozlabs.org >Subject: RE: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error >management registers > > > >>-----Original Message----- >>From: Xie Shaohui-B21989 >>Sent: Thursday, July 21, 2011 6:30 PM >>To: linuxppc-dev@lists.ozlabs.org >>Cc: Gala Kumar-B11780; Jiang Kai-B18973; Kumar Gala; Xie Shaohui-B21989 >>Subject: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error >>management registers >> >>From: Kai.Jiang <Kai.Jiang@freescale.com> >> >>There are some differences of register offset and definition between >>pci and pcie error management registers. While, some other pci/pcie >>error management registers are nearly the same. >> >>Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> >>Signed-off-by: Kumar Gala <galak@kernel.crashing.org> >>Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> >>--- >> arch/powerpc/sysdev/fsl_pci.h | 31 +++++++++++++++++++++++++------ >> 1 files changed, 25 insertions(+), 6 deletions(-) >> >>difg --gite a/arch/powerpc/sysdev/fsl_pci.h >>b/arch/powerpc/sysdev/fsl_pci.h index a39ed5c..60a76e9 100644 >>--- a/arch/powerpc/sysdev/fsl_pci.h >>+++ b/arch/powerpc/sysdev/fsl_pci.h >>@@ -74,13 +74,32 @@ struct ccsr_pci { >> */ >> struct pci_inbound_window_regs piw[4]; >> >>+/* Merge PCI/PCI Express error management registers */ >> __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect >>register */ >>- u8 res21[4]; >>- __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt >>enable register */ >>- u8 res22[4]; >>- __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error >>disable register */ >>- u8 res23[12]; >>- __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture >>status register */ >>+ __be32 pex_err_cap_dr; /* 0x.e04 */ >>+ /* - PCI error capture disabled register */ >>+ /* - PCIE has no this register */ >>+ __be32 pex_err_en; /* 0x.e08 */ >>+ /* - PCI/PCIE error interrupt enable >>register*/ >>+ __be32 pex_err_attrib; /* 0x.e0c */ >>+ /* - PCI error attributes capture register >>*/ >>+ /* - PCIE has no this register */ >>+ __be32 pex_err_disr; /* 0x.e10 */ >>+ /* - PCI error address capture register */ >>+ /* - PCIE error disable register */ >>+ __be32 pex_err_ext_addr; /* 0x.e14 */ >>+ /* - PCI error extended addr capture >>register*/ >>+ /* - PCIE has no this register */ >>+ __be32 pex_err_dl; /* 0x.e18 */ >>+ /* - PCI error data low capture register */ >>+ /* - PCIE has no this register */ >>+ __be32 pex_err_dh; /* 0x.e1c */ >>+ /* - PCI error data high capture register */ >>+ /* - PCIE has no this register */ >>+ __be32 pex_err_cap_stat; /* 0x.e20 */ >>+ /* - PCI gasket timer register */ >>+ /* - PCIE error capture status register */ >>+ >> u8 res24[4]; >> __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture >>register 0 */ >> __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture >>register 0 */ >>-- >>1.6.4 >[Xie Shaohui] I've verified this patch can apply for galak/powerpc.git >'next' branch with no change. > > >Best Regards, >Shaohui Xie
--- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -74,13 +74,32 @@ struct ccsr_pci { */ struct pci_inbound_window_regs piw[4]; +/* Merge PCI/PCI Express error management registers */ __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ - u8 res21[4]; - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ - u8 res22[4]; - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ - u8 res23[12]; - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ + __be32 pex_err_cap_dr; /* 0x.e04 */ + /* - PCI error capture disabled register */ + /* - PCIE has no this register */ + __be32 pex_err_en; /* 0x.e08 */ + /* - PCI/PCIE error interrupt enable register*/ + __be32 pex_err_attrib; /* 0x.e0c */ + /* - PCI error attributes capture register */ + /* - PCIE has no this register */ + __be32 pex_err_disr; /* 0x.e10 */ + /* - PCI error address capture register */ + /* - PCIE error disable register */ + __be32 pex_err_ext_addr; /* 0x.e14 */ + /* - PCI error extended addr capture register*/ + /* - PCIE has no this register */ + __be32 pex_err_dl; /* 0x.e18 */ + /* - PCI error data low capture register */ + /* - PCIE has no this register */ + __be32 pex_err_dh; /* 0x.e1c */ + /* - PCI error data high capture register */ + /* - PCIE has no this register */ + __be32 pex_err_cap_stat; /* 0x.e20 */ + /* - PCI gasket timer register */ + /* - PCIE error capture status register */ + u8 res24[4]; __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */