From patchwork Tue Jun 14 13:54:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 100333 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 76895B74C0 for ; Wed, 15 Jun 2011 00:05:48 +1000 (EST) Received: by ozlabs.org (Postfix) id C94D8B6FBE; Wed, 15 Jun 2011 00:05:37 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from gw1.transmode.se (gw1.transmode.se [195.58.98.146]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6AB7DB6FBD for ; Wed, 15 Jun 2011 00:05:37 +1000 (EST) Received: from mail1.transmode.se (mail1.transmode.se [192.168.201.18]) by gw1.transmode.se (Postfix) with ESMTP id 40C26258055; Tue, 14 Jun 2011 15:55:20 +0200 (CEST) Received: from gentoo-jocke.transmode.se ([172.20.4.10]) by mail1.transmode.se (Lotus Domino Release 8.5.2FP2) with ESMTP id 2011061415551930-76953 ; Tue, 14 Jun 2011 15:55:19 +0200 Received: from gentoo-jocke.transmode.se (localhost [127.0.0.1]) by gentoo-jocke.transmode.se (8.14.4/8.14.0) with ESMTP id p5EDtKwQ010932; Tue, 14 Jun 2011 15:55:20 +0200 Received: (from jocke@localhost) by gentoo-jocke.transmode.se (8.14.4/8.14.4/Submit) id p5EDtKN9010931; Tue, 14 Jun 2011 15:55:20 +0200 From: Joakim Tjernlund To: Willy Tarreau , Scott Wood , linuxppc-dev Subject: [PATCH 06/15] 8xx: Always pin kernel instruction TLB Date: Tue, 14 Jun 2011 15:54:51 +0200 Message-Id: <1308059700-10839-7-git-send-email-Joakim.Tjernlund@transmode.se> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se> References: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se> X-MIMETrack: Itemize by SMTP Server on mail1/Transmode(Release 8.5.2FP2|March 22, 2011) at 06/14/2011 15:55:19, Serialize by Router on mail1/Transmode(Release 8.5.2FP2|March 22, 2011) at 06/14/2011 15:55:19, Serialize complete at 06/14/2011 15:55:19 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index c9770b6..48e9dde 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -785,12 +785,13 @@ start_here: */ initial_mmu: tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB + +/* Always pin the first 8 MB ITLB to prevent ITLB + misses while mucking around with SRR0/SRR1 in asm +*/ lis r8, MI_RSV4I@h ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif + mtspr MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB