From patchwork Mon May 23 06:21:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 96823 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 74807B74DE for ; Mon, 23 May 2011 16:23:03 +1000 (EST) Received: from AM1EHSOBE004.bigfish.com (am1ehsobe004.messaging.microsoft.com [213.199.154.207]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Cybertrust SureServer Standard Validation CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 0DD56B6FAF for ; Mon, 23 May 2011 16:22:52 +1000 (EST) Received: from mail3-am1-R.bigfish.com (10.3.201.251) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 14.1.225.22; Mon, 23 May 2011 06:22:45 +0000 Received: from mail3-am1 (localhost.localdomain [127.0.0.1]) by mail3-am1-R.bigfish.com (Postfix) with ESMTP id 27DC4C408F6; Mon, 23 May 2011 06:22:45 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail3-am1 (localhost.localdomain [127.0.0.1]) by mail3-am1 (MessageSwitch) id 1306131756662114_10761; Mon, 23 May 2011 06:22:36 +0000 (UTC) Received: from AM1EHSMHS018.bigfish.com (unknown [10.3.201.242]) by mail3-am1.bigfish.com (Postfix) with ESMTP id BC041FC809E; Mon, 23 May 2011 06:22:00 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS018.bigfish.com (10.3.206.21) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 23 May 2011 06:21:55 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.270.2; Mon, 23 May 2011 01:21:54 -0500 Received: from lc1106.zin33.ap.freescale.net (lc1106.zin33.ap.freescale.net [10.232.3.106]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p4N6LrO6001228; Mon, 23 May 2011 01:21:54 -0500 (CDT) Received: by lc1106.zin33.ap.freescale.net (Postfix, from userid 65011241) id 7DD26C06B; Mon, 23 May 2011 11:51:52 +0530 (IST) From: Prabhakar Kushwaha To: Subject: [PATCH][v2] powerpc/85xx: add host-pci(e) bridge only for RC Date: Mon, 23 May 2011 11:51:46 +0530 Message-ID: <1306131706-15385-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.6.5.6 MIME-Version: 1.0 X-OriginatorOrg: freescale.net Cc: meet2prabhu@gmail.com, Vivek Mahajan , Prabhakar Kushwaha X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org FSL PCIe controller can act as agent(EP) or host(RC). Under Agent(EP) mode they are configured via Host. So it is not required to add with the PCI(e) sub-system. Add and configure PCIe controller only for RC mode. Signed-off-by: Vivek Mahajan Signed-off-by: Prabhakar Kushwaha --- Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master) Chages for v2: Incorporated Kumar's comment - Use PCI_CLASS_PROG instead of PCI_HEADER_TYPE arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 68ca929..4a1d37c 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) struct pci_controller *hose; struct resource rsrc; const int *bus_range; + u8 progif; if (!of_device_is_available(dev)) { pr_warning("%s: disabled\n", dev->full_name); @@ -353,6 +354,19 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, PPC_INDIRECT_TYPE_BIG_ENDIAN); + + early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); + if (progif & 1 ) { + u32 temp; + + temp = (u32)hose->cfg_data & ~PAGE_MASK; + if (((u32)hose->cfg_data & PAGE_MASK) != (u32)hose->cfg_addr) + iounmap(hose->cfg_data - temp); + iounmap(hose->cfg_addr); + pcibios_free_controller(hose); + return 0; + } + setup_pci_cmd(hose); /* check PCI express link status */