From patchwork Fri Feb 25 21:59:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meador Inge X-Patchwork-Id: 84577 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id F1C55B7954 for ; Sat, 26 Feb 2011 09:01:23 +1100 (EST) Received: from relay1.mentorg.com (relay1.mentorg.com [192.94.38.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "relay1.mentorg.com", Issuer "Entrust Certification Authority - L1B" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 61D70B70F8; Sat, 26 Feb 2011 09:00:20 +1100 (EST) Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1Pt5hx-0006vG-PN from meador_inge@mentor.com ; Fri, 25 Feb 2011 14:00:17 -0800 Received: from na2-mail.mgc.mentorg.com ([134.86.114.213]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 25 Feb 2011 14:00:17 -0800 Received: from localhost.localdomain ([134.86.101.95]) by na2-mail.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 25 Feb 2011 15:00:16 -0700 From: Meador Inge To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 1/2] powerpc: document the Open PIC device tree binding Date: Fri, 25 Feb 2011 15:59:36 -0600 Message-Id: <1298671177-19572-2-git-send-email-meador_inge@mentor.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1298671177-19572-1-git-send-email-meador_inge@mentor.com> References: <1298671177-19572-1-git-send-email-meador_inge@mentor.com> X-OriginalArrivalTime: 25 Feb 2011 22:00:16.0744 (UTC) FILETIME=[62C8DE80:01CBD537] Cc: devicetree-discuss@lists.ozlabs.org, Hollis Blanchard , Stuart Yoder X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This binding documents several properties that have been in use for quite some time, and adds one new property 'pic-no-reset', which controls the runtime initialization behavior of the PIC. More specifically, the presence of 'pic-no-reset' mandates that the PIC shall not be reset during runtime initialization and that any initialization related to interrupt sources shall be limited to sources explicitly referenced in the device tree. This functionality is useful in AMP systems where multiple OSes are sharing the PIC and the reinitialization of the PIC can interfere with OSes that are already up and running. The interrupt specifier definition is based off of Stuart Yoder's FSL MPIC binding. Signed-off-by: Meador Inge Cc: Hollis Blanchard Cc: Stuart Yoder --- Documentation/powerpc/dts-bindings/open-pic.txt | 98 +++++++++++++++++++++++ 1 files changed, 98 insertions(+), 0 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/open-pic.txt diff --git a/Documentation/powerpc/dts-bindings/open-pic.txt b/Documentation/powerpc/dts-bindings/open-pic.txt new file mode 100644 index 0000000..909a902 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/open-pic.txt @@ -0,0 +1,98 @@ +* Open PIC Binding + +This binding specifies what properties must be available in the device tree +representation of an Open PIC compliant interrupt controller. This binding is +based on the binding defined for Open PIC in [1] and is a superset of that +binding. + +Required properties: + + NOTE: Many of these descriptions were paraphrased here from [1] to aid + readability. + + - compatible: Specifies the compatibility list for the PIC. The type + shall be and the value shall include "open-pic". + + - reg: Specifies the base physical address(s) and size(s) of this + PIC's addressable register space. The type shall be . + + - interrupt-controller: The presence of this property identifies the node + as an Open PIC. No property value shall be defined. + + - #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 2. + + - #address-cells: Specifies the number of cells needed to encode an + address. The type shall be and the value shall be 0. As such, + 'interrupt-map' nodes do not have to specify a parent unit address. + +Optional properties: + + - pic-no-reset: The presence of this property indicates that the PIC + shall not be reset during runtime initialization. No property value shall + be defined. The presence of this property also mandates that any + initialization related to interrupt sources shall be limited to sources + explicitly referenced in the device tree. + +* Interrupt Specifier Definition + + Interrupt specifiers consists of 2 cells encoded as + follows: + + - <1st-cell>: The interrupt-number that identifies the interrupt source. + + - <2nd-cell>: The level-sense information, encoded as follows: + 0 = low-to-high edge triggered + 1 = active low level-sensitive + 2 = active high level-sensitive + 3 = high-to-low edge triggered + +* Examples + +Example 1: + + /* + * An Open PIC interrupt controller + */ + mpic: pic@40000 { + // This is an interrupt controller node. + interrupt-controller; + + // No address cells so that 'interrupt-map' nodes which reference + // this Open PIC node do not need a parent address specifier. + #address-cells = <0>; + + // Two cells to encode interrupt sources. + #interrupt-cells = <2>; + + // Offset address of 0x40000 and size of 0x40000. + reg = <0x40000 0x40000>; + + // Compatible with Open PIC. + compatible = "open-pic"; + + // The PIC shall not be reset. + pic-no-reset; + }; + +Example 2: + + /* + * An interrupt generating device that is wired to an Open PIC. + */ + serial0: serial@4500 { + // Interrupt source '42' that is active high level-sensitive. + // Note that there are only two cells as specified in the interrupt + // parent's '#interrupt-cells' property. + interrupts = <42 2>; + + // The interrupt controller that this device is wired to. + interrupt-parent = <&mpic>; + }; + +* References + +[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform + Requirements (ePAPR), Version 1.0, July 2008. + (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf) +