From patchwork Thu Jul 20 00:29:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 791311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rere.qmqm.pl header.i=@rere.qmqm.pl header.b="PJN8zr7O"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xCZXR6ysdz9t33 for ; Thu, 20 Jul 2017 10:29:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754205AbdGTA30 (ORCPT ); Wed, 19 Jul 2017 20:29:26 -0400 Received: from rere.qmqm.pl ([91.227.64.183]:50900 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753598AbdGTA3Z (ORCPT ); Wed, 19 Jul 2017 20:29:25 -0400 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 2541A328; Thu, 20 Jul 2017 02:29:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1500510564; bh=iH8YRKC/31iaqNZoqcchDjX77UUyo3FLtPc+v+RfjDA=; h=Date:In-Reply-To:References:From:Subject:To:From; b=PJN8zr7OJfcl07yGwcq8u8D3JGPY/LGhT+GnYEzuHXEg3sgIJhmKLChqRDkpkqfZR bxRzxRcgVU5lm3O11yucfSftJntjJaBmTpJxGQl2Z3RBtbQsd8tWEJw4tvEN4gYNER CjZY6OXuzIwJ8LTUXiFV9ouafCv6dfefgVEOHXTpG9vpGf5je8YfGzVHLDE9kGZ0UQ hmq1EEoxhiO7ORcItX44m9NBBc1HfJyR5kft6T0qRqB4MJ+mofLApqY1UJk2Oq70XZ ZIgF32PExn+SwtKB8tvR1Mz+oK7LS+EvtOxNah5ZLg7S4aIdpePFvMNCK/HhHIR+oj S1zgOnd1a6VHw== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99.2 at rere Date: Thu, 20 Jul 2017 02:29:23 +0200 Message-Id: In-Reply-To: References: From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH 3/9] arm: cache-l2x0: share l2x0_base MIME-Version: 1.0 To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Share l2x0_base between cache-l2x0 and pmu drivers. They are duplicates. Signed-off-by: Michał Mirosław --- arch/arm/include/asm/hardware/cache-l2x0.h | 5 +++-- arch/arm/mm/cache-l2x0-pmu.c | 8 ++------ arch/arm/mm/cache-l2x0.c | 4 ++-- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 736292b42fca..492de655e4f3 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -167,11 +167,11 @@ static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) #endif #ifdef CONFIG_CACHE_L2X0_PMU -void l2x0_pmu_register(void __iomem *base, u32 part); +void l2x0_pmu_register(u32 part); void l2x0_pmu_suspend(void); void l2x0_pmu_resume(void); #else -static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} +static inline void l2x0_pmu_register(u32 part) {} static inline void l2x0_pmu_suspend(void) {} static inline void l2x0_pmu_resume(void) {} #endif @@ -193,6 +193,7 @@ struct l2x0_regs { unsigned long aux2_ctrl; }; +extern void __iomem *l2x0_base; extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index 0a1e2280141f..1f36801d337f 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -29,7 +29,6 @@ #define PMU_NR_COUNTERS 2 -static void __iomem *l2x0_base; static struct pmu *l2x0_pmu; static cpumask_t pmu_cpu; @@ -491,7 +490,7 @@ void l2x0_pmu_resume(void) l2x0_pmu_enable(l2x0_pmu); } -void __init l2x0_pmu_register(void __iomem *base, u32 part) +void __init l2x0_pmu_register(u32 part) { /* * Determine whether we support the PMU, and choose the name for sysfs. @@ -503,8 +502,7 @@ void __init l2x0_pmu_register(void __iomem *base, u32 part) * supported by this driver. * * We must defer registering the PMU until the perf subsystem is up and - * running, so just stash the name and base, and leave that to another - * initcall. + * running, so just stash the name, and leave that to another initcall. */ switch (part & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L220: @@ -516,8 +514,6 @@ void __init l2x0_pmu_register(void __iomem *base, u32 part) default: return; } - - l2x0_base = base; } static __init int l2x0_pmu_init(void) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ea1e70ff4568..bbfbc18399f9 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -48,13 +48,13 @@ struct l2c_init_data { #define CACHE_LINE_SIZE 32 -static void __iomem *l2x0_base; static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; +void __iomem *l2x0_base; struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -900,7 +900,7 @@ static int __init __l2c_init(const struct l2c_init_data *data, pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", data->type, cache_id, aux); - l2x0_pmu_register(l2x0_base, cache_id); + l2x0_pmu_register(cache_id); return 0; }