| Message ID | ae44d3c1f4ceecb0f6a486d569608eec3c892ba1.1353104179.git.marvin24@gmx.de |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Fri, Nov 16, 2012 at 11:20:55PM +0100, Marc Dietrich wrote: > This adds host1x support which includes HDMI and LVDS support. > > Signed-off-by: Marc Dietrich <marvin24@gmx.de> > --- > arch/arm/boot/dts/tegra20-paz00.dts | 27 ++++++++++++++++++++++----- > 1 file changed, 22 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts > index e884fa5..3f7f5a2 100644 > --- a/arch/arm/boot/dts/tegra20-paz00.dts > +++ b/arch/arm/boot/dts/tegra20-paz00.dts > @@ -244,7 +244,7 @@ > clock-frequency = <216000000>; > }; > > - i2c@7000c000 { > + lvds_ddc: i2c@7000c000 { > status = "okay"; > clock-frequency = <400000>; You might want to change this to 100 kHz as well. I think some displays don't like fast mode. Then again, if you've verified that this works on AC100 I suppose it can just as well stay as is. On a side-note, I've found that Tegra doesn't do proper 400 kHz either, but rather something like 375 kHz. Stephen, is this a known issue or is it actually supposed to be able to do exactly 400 kHz? > > @@ -256,9 +256,9 @@ > }; > }; > > - i2c@7000c400 { > + hdmi_ddc: i2c@7000c400 { > status = "okay"; > - clock-frequency = <400000>; > + clock-frequency = <100000>; > }; > > nvec { > @@ -399,13 +399,13 @@ > regulator-max-microvolt = <1800000>; > }; > > - ldo7 { > + hdmi_vdd_reg: ldo7 { > regulator-name = "+3.3vs_ldo7,avdd_hdmi"; > regulator-min-microvolt = <3300000>; > regulator-max-microvolt = <3300000>; > }; > > - ldo8 { > + hdmi_pll_reg: ldo8 { > regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; > regulator-min-microvolt = <1800000>; > regulator-max-microvolt = <1800000>; > @@ -499,6 +499,23 @@ > }; > }; > > + host1x { The host1x node should be sorted earlier, according to its bus address. > + dc@54200000 { > + rgb { > + status = "okay"; > + nvidia,ddc-i2c-bus = <&lvds_ddc>; > + }; > + }; > + > + hdmi { > + status = "okay"; > + vdd-supply = <&hdmi_vdd_reg>; > + pll-supply = <&hdmi_pll_reg>; > + nvidia,ddc-i2c-bus = <&hdmi_ddc>; > + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ > + }; > + }; As Stephen already mentioned, and I think you already experienced, tegra-drm has issues with two enabled outputs that run at different resolutions, so you should probably keep HDMI disabled for now. Thierry
On 11/16/2012 03:20 PM, Marc Dietrich wrote: > This adds host1x support which includes HDMI and LVDS support. > diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts > + host1x { The position of this node in tegra20-paz00.dts doesn't match the order from tegra20.dtsi. > + dc@54200000 { > + rgb { > + status = "okay"; > + nvidia,ddc-i2c-bus = <&lvds_ddc>; > + }; > + }; > + > + hdmi { > + status = "okay"; > + vdd-supply = <&hdmi_vdd_reg>; > + pll-supply = <&hdmi_pll_reg>; > + nvidia,ddc-i2c-bus = <&hdmi_ddc>; > + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ > + }; I think we shouldn't enable HDMI on Paz00 yet; tegradrm has an issue where if two outputs are active, with different display timings (which is almost guaranteed), both outputs send the wrong signal timing. The easiest WAR for now is to only enable one output per board. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 11/16/2012 03:35 PM, Thierry Reding wrote: > On Fri, Nov 16, 2012 at 11:20:55PM +0100, Marc Dietrich wrote: >> This adds host1x support which includes HDMI and LVDS support. >> diff --git a/arch/arm/boot/dts/tegra20-paz00.dts >> b/arch/arm/boot/dts/tegra20-paz00.dts >> - i2c@7000c000 { + lvds_ddc: i2c@7000c000 { status = "okay"; >> clock-frequency = <400000>; > > You might want to change this to 100 kHz as well. I think some > displays don't like fast mode. Then again, if you've verified that > this works on AC100 I suppose it can just as well stay as is. > > On a side-note, I've found that Tegra doesn't do proper 400 kHz > either, but rather something like 375 kHz. Stephen, is this a known > issue or is it actually supposed to be able to do exactly 400 kHz? 400KHz is the maximum clock per fast mode spec. The bus should work anywhere down to 0Hz without issue. The fact we don't hit 400KHz is most likely simply due to granularity of the clock divider for the I2C block, combined with whatever rate the parent runs at. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Nov 16, 2012 at 03:36:04PM -0700, Stephen Warren wrote: > On 11/16/2012 03:20 PM, Marc Dietrich wrote: > > This adds host1x support which includes HDMI and LVDS support. > > > diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts > > > + host1x { > > The position of this node in tegra20-paz00.dts doesn't match the order > from tegra20.dtsi. > > > + dc@54200000 { > > + rgb { > > + status = "okay"; > > + nvidia,ddc-i2c-bus = <&lvds_ddc>; > > + }; > > + }; > > + > > + hdmi { > > + status = "okay"; > > + vdd-supply = <&hdmi_vdd_reg>; > > + pll-supply = <&hdmi_pll_reg>; > > + nvidia,ddc-i2c-bus = <&hdmi_ddc>; > > + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ > > + }; > > I think we shouldn't enable HDMI on Paz00 yet; tegradrm has an issue > where if two outputs are active, with different display timings (which > is almost guaranteed), both outputs send the wrong signal timing. The > easiest WAR for now is to only enable one output per board. I don't think the timings are the problem. At least in the cases where I've seen this problem, LVDS was still working fine, only the contents were "skewed". The most likely reason for that would be a wrong stride programmed for the smaller display. But yes, I agree that for now we should keep only a single output enabled to work around that issue. Unless I get completely swamped with other stuff I expect to fix that before the final 3.8, but better safe than sorry. Thierry
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index e884fa5..3f7f5a2 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -244,7 +244,7 @@ clock-frequency = <216000000>; }; - i2c@7000c000 { + lvds_ddc: i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -256,9 +256,9 @@ }; }; - i2c@7000c400 { + hdmi_ddc: i2c@7000c400 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; }; nvec { @@ -399,13 +399,13 @@ regulator-max-microvolt = <1800000>; }; - ldo7 { + hdmi_vdd_reg: ldo7 { regulator-name = "+3.3vs_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + hdmi_pll_reg: ldo8 { regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -499,6 +499,23 @@ }; }; + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,ddc-i2c-bus = <&lvds_ddc>; + }; + }; + + hdmi { + status = "okay"; + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + sound { compatible = "nvidia,tegra-audio-alc5632-paz00", "nvidia,tegra-audio-alc5632";
This adds host1x support which includes HDMI and LVDS support. Signed-off-by: Marc Dietrich <marvin24@gmx.de> --- arch/arm/boot/dts/tegra20-paz00.dts | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-)