| Message ID | 20240402132626.24693-2-sumitg@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | memory: tegra: Skip restricted register access from Guest | expand |
On Tue, 02 Apr 2024 18:56:25 +0530, Sumit Gupta wrote: > MC SID and Broadbast channel register access is restricted for Guest VM. > Make both the regions as optional for SoC's from Tegra186 onwards. > Tegra MC driver will skip access to the restricted registers from Guest > if the respective regions are not present in the memory-controller node > of Guest DT. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg: [[0, 46137344, 0, 65536], [0, 46202880, 0, 65536], [0, 46268416, 0, 65536], [0, 46333952, 0, 65536], [0, 46399488, 0, 65536], [0, 46465024, 0, 65536]] is too long from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:0: 'ch0' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:1: 'ch1' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:2: 'ch2' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:3: 'ch3' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:4: 'sid' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.example.dtb: memory-controller@2c00000: reg-names:5: 'broadcast' was expected from schema $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240402132626.24693-2-sumitg@nvidia.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 02/04/2024 14:26, Sumit Gupta wrote: > MC SID and Broadbast channel register access is restricted for Guest VM. > Make both the regions as optional for SoC's from Tegra186 onwards. > Tegra MC driver will skip access to the restricted registers from Guest > if the respective regions are not present in the memory-controller node > of Guest DT. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > index 935d63d181d9..c52c259f7ec5 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > @@ -146,17 +146,17 @@ allOf: > then: > properties: > reg: > - maxItems: 6 > + maxItems: 4 minItems? Jon
On 02/04/2024 21:15, Jon Hunter wrote: > > > On 02/04/2024 14:26, Sumit Gupta wrote: >> MC SID and Broadbast channel register access is restricted for Guest VM. >> Make both the regions as optional for SoC's from Tegra186 onwards. >> Tegra MC driver will skip access to the restricted registers from Guest >> if the respective regions are not present in the memory-controller node >> of Guest DT. >> >> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> >> --- >> .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- >> 1 file changed, 9 insertions(+), 9 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> index 935d63d181d9..c52c259f7ec5 100644 >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >> @@ -146,17 +146,17 @@ allOf: >> then: >> properties: >> reg: >> - maxItems: 6 >> + maxItems: 4 > > minItems? > If the intention was to make it variable, then yes, missing minItems. But more important: why patch was sent without any testing? Best regards, Krzysztof
>> >> On 02/04/2024 14:26, Sumit Gupta wrote: >>> MC SID and Broadbast channel register access is restricted for Guest VM. >>> Make both the regions as optional for SoC's from Tegra186 onwards. >>> Tegra MC driver will skip access to the restricted registers from Guest >>> if the respective regions are not present in the memory-controller node >>> of Guest DT. >>> >>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> >>> --- >>> .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- >>> 1 file changed, 9 insertions(+), 9 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>> index 935d63d181d9..c52c259f7ec5 100644 >>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml >>> @@ -146,17 +146,17 @@ allOf: >>> then: >>> properties: >>> reg: >>> - maxItems: 6 >>> + maxItems: 4 >> >> minItems? >> > > If the intention was to make it variable, then yes, missing minItems. > But more important: why patch was sent without any testing? > > Best regards, > Krzysztof > I tested yaml file after doing the change for Tegra194 and Tegra234. Changed the Tegra186 entry later and didn't verify that. My bad as missed the obvious. Will correct the yaml file and send v3. Will wait if any comments on 'Patch 2' before sending v3. Best Regards, Sumit Gupta
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 935d63d181d9..c52c259f7ec5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -146,17 +146,17 @@ allOf: then: properties: reg: - maxItems: 6 + maxItems: 4 description: 5 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - const: ch0 - const: ch1 - const: ch2 - const: ch3 + - const: sid + - const: broadcast - if: properties: @@ -165,13 +165,11 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - const: ch0 - const: ch1 - const: ch2 @@ -188,6 +186,8 @@ allOf: - const: ch13 - const: ch14 - const: ch15 + - const: sid + - const: broadcast - if: properties: @@ -196,13 +196,11 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - const: ch0 - const: ch1 - const: ch2 @@ -219,6 +217,8 @@ allOf: - const: ch13 - const: ch14 - const: ch15 + - const: sid + - const: broadcast additionalProperties: false
MC SID and Broadbast channel register access is restricted for Guest VM. Make both the regions as optional for SoC's from Tegra186 onwards. Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)