| Message ID | 20240116115838.16544-2-pohsuns@nvidia.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clocksource: fix Tegra234 SoC Watchdog Timer. | expand |
Hi Pohsun, kernel test robot noticed the following build errors: [auto build test ERROR on tip/timers/core] [also build test ERROR on linus/master v6.7 next-20240117] [cannot apply to daniel-lezcano/clockevents/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Pohsun-Su/clocksource-drivers-timer-tegra186-add-WDIOC_GETTIMELEFT-support/20240116-200217 base: tip/timers/core patch link: https://lore.kernel.org/r/20240116115838.16544-2-pohsuns%40nvidia.com patch subject: [PATCH 1/2] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20240117/202401172015.KdPd7tda-lkp@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240117/202401172015.KdPd7tda-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202401172015.KdPd7tda-lkp@intel.com/ All errors (new ones prefixed by >>): drivers/clocksource/timer-tegra186.c: In function 'tegra186_wdt_get_timeleft': >> drivers/clocksource/timer-tegra186.c:263:22: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration] 263 | expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, readl_relaxed(wdt->regs + WDTSR)); | ^~~~~~~~~ cc1: some warnings being treated as errors vim +/FIELD_GET +263 drivers/clocksource/timer-tegra186.c 240 241 static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) 242 { 243 struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); 244 u32 timeleft; 245 u32 expiration; 246 247 if (!watchdog_active(&wdt->base)) { 248 /* return zero if the watchdog timer is not activated. */ 249 return 0; 250 } 251 252 /* 253 * System power-on reset occurs on the fifth expiration of the watchdog timer and so 254 * when the watchdog timer is configured, the actual value programmed into the counter 255 * is 1/5 of the timeout value. Once the counter reaches 0, expiration count will be 256 * increased by 1 and the down counter restarts. 257 * Hence to get the time left before system reset we must combine 2 parts: 258 * 1. value of the current down counter 259 * 2. (number of counter expirations remaining) * (timeout/5) 260 */ 261 262 /* Get the current number of counter expirations. Should be a value between 0 and 4. */ > 263 expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, readl_relaxed(wdt->regs + WDTSR)); 264 265 /* Convert the current counter value to seconds, rounding up to the nearest second. */ 266 timeleft = FIELD_GET(TMRSR_PCV, readl_relaxed(wdt->tmr->regs + TMRSR)); 267 timeleft = (timeleft + USEC_PER_SEC / 2) / USEC_PER_SEC; 268 269 /* 270 * Calculate the time remaining by adding the time for the counter value 271 * to the time of the counter expirations that remain. 272 */ 273 timeleft += wdt->base.timeout * (4 - expiration) / 5; 274 return timeleft; 275 } 276
diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index 304537dadf2c..685c6689a2da 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -29,6 +29,7 @@ #define TMRSR 0x004 #define TMRSR_INTR_CLR BIT(30) +#define TMRSR_PCV GENMASK(28, 0) #define TMRCSSR 0x008 #define TMRCSSR_SRC_USEC (0 << 0) @@ -45,6 +46,9 @@ #define WDTCR_TIMER_SOURCE_MASK 0xf #define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) +#define WDTSR 0x004 +#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12) + #define WDTCMDR 0x008 #define WDTCMDR_DISABLE_COUNTER BIT(1) #define WDTCMDR_START_COUNTER BIT(0) @@ -234,12 +238,49 @@ static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, return 0; } +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + u32 timeleft; + u32 expiration; + + if (!watchdog_active(&wdt->base)) { + /* return zero if the watchdog timer is not activated. */ + return 0; + } + + /* + * System power-on reset occurs on the fifth expiration of the watchdog timer and so + * when the watchdog timer is configured, the actual value programmed into the counter + * is 1/5 of the timeout value. Once the counter reaches 0, expiration count will be + * increased by 1 and the down counter restarts. + * Hence to get the time left before system reset we must combine 2 parts: + * 1. value of the current down counter + * 2. (number of counter expirations remaining) * (timeout/5) + */ + + /* Get the current number of counter expirations. Should be a value between 0 and 4. */ + expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, readl_relaxed(wdt->regs + WDTSR)); + + /* Convert the current counter value to seconds, rounding up to the nearest second. */ + timeleft = FIELD_GET(TMRSR_PCV, readl_relaxed(wdt->tmr->regs + TMRSR)); + timeleft = (timeleft + USEC_PER_SEC / 2) / USEC_PER_SEC; + + /* + * Calculate the time remaining by adding the time for the counter value + * to the time of the counter expirations that remain. + */ + timeleft += wdt->base.timeout * (4 - expiration) / 5; + return timeleft; +} + static const struct watchdog_ops tegra186_wdt_ops = { .owner = THIS_MODULE, .start = tegra186_wdt_start, .stop = tegra186_wdt_stop, .ping = tegra186_wdt_ping, .set_timeout = tegra186_wdt_set_timeout, + .get_timeleft = tegra186_wdt_get_timeleft, }; static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra,
This change adds support for WDIOC_GETTIMELEFT so userspace programs can get the number of seconds before system reset by the watchdog timer via ioctl. Signed-off-by: Pohsun Su <pohsuns@nvidia.com> --- drivers/clocksource/timer-tegra186.c | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)