| Message ID | 20231213122030.11734-5-akhilrajeev@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show
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Wed, 13 Dec 2023 04:21:41 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 13 Dec 2023 04:21:41 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Wed, 13 Dec 2023 04:21:39 -0800 From: Akhil R <akhilrajeev@nvidia.com> To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>, <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <linux-tegra@vger.kernel.org> CC: Akhil R <akhilrajeev@nvidia.com> Subject: [PATCH 4/5] arm64: defconfig: Enable Tegra Security Engine Date: Wed, 13 Dec 2023 17:50:29 +0530 Message-ID: <20231213122030.11734-5-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231213122030.11734-1-akhilrajeev@nvidia.com> References: <20231213122030.11734-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: <linux-tegra.vger.kernel.org> List-Subscribe: <mailto:linux-tegra+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-tegra+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|DM4PR12MB6038:EE_ X-MS-Office365-Filtering-Correlation-Id: 35448e40-1020-4d88-8bc1-08dbfbd61628 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add Tegra Security Engine driver
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expand
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diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b130e6b74003..60a098e2a691 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1594,6 +1594,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m CONFIG_CRYPTO_DEV_QCE=m CONFIG_CRYPTO_DEV_QCOM_RNG=m +CONFIG_CRYPTO_DEV_TEGRA=m CONFIG_CRYPTO_DEV_CCREE=m CONFIG_CRYPTO_DEV_HISI_SEC2=m CONFIG_CRYPTO_DEV_HISI_ZIP=m
Enable Tegra Security Engine which can accelerate various AES and HASH algorithms on supported hardware. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)