| Message ID | 20220516100213.1536571-3-cyndis@kapsi.fi |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Host1x support on Tegra234 | expand |
On 16/05/2022 12:02, cyndis@kapsi.fi wrote: > From: Mikko Perttunen <mperttunen@nvidia.com> > > Add clock, memory controller, powergate and reset dt-binding headers > for Host1x and VIC on Tegra234. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> All your patches are send from wrong email address and the SoB chain is not correct. Please add respective SoB. This applies to entire patchset. Best regards, Krzysztof
On 5/17/22 11:02, Krzysztof Kozlowski wrote: > On 16/05/2022 12:02, cyndis@kapsi.fi wrote: >> From: Mikko Perttunen <mperttunen@nvidia.com> >> >> Add clock, memory controller, powergate and reset dt-binding headers >> for Host1x and VIC on Tegra234. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > > All your patches are send from wrong email address and the SoB chain is > not correct. Please add respective SoB. > > This applies to entire patchset. > > > Best regards, > Krzysztof I can do Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Mikko Perttunen <cyndis@kapsi.fi> if that is better. I used to just send with From: mperttunen@nvidia.com but unsurprisingly many mail servers have started rejecting that. Mikko
On 17/05/2022 10:41, Mikko Perttunen wrote: > On 5/17/22 11:02, Krzysztof Kozlowski wrote: >> On 16/05/2022 12:02, cyndis@kapsi.fi wrote: >>> From: Mikko Perttunen <mperttunen@nvidia.com> >>> >>> Add clock, memory controller, powergate and reset dt-binding headers >>> for Host1x and VIC on Tegra234. >>> >>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> >> All your patches are send from wrong email address and the SoB chain is >> not correct. Please add respective SoB. >> >> This applies to entire patchset. >> >> >> Best regards, >> Krzysztof > > I can do > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > Signed-off-by: Mikko Perttunen <cyndis@kapsi.fi> > > if that is better. That's not needed, if your name was in the sender field. The trouble is that your name was not there and I have no clue who is cyndis@kapsi.fi. Best regards, Krzysztof
On 5/17/22 11:43, Krzysztof Kozlowski wrote: > On 17/05/2022 10:41, Mikko Perttunen wrote: >> On 5/17/22 11:02, Krzysztof Kozlowski wrote: >>> On 16/05/2022 12:02, cyndis@kapsi.fi wrote: >>>> From: Mikko Perttunen <mperttunen@nvidia.com> >>>> >>>> Add clock, memory controller, powergate and reset dt-binding headers >>>> for Host1x and VIC on Tegra234. >>>> >>>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >>> >>> All your patches are send from wrong email address and the SoB chain is >>> not correct. Please add respective SoB. >>> >>> This applies to entire patchset. >>> >>> >>> Best regards, >>> Krzysztof >> >> I can do >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> Signed-off-by: Mikko Perttunen <cyndis@kapsi.fi> >> >> if that is better. > > That's not needed, if your name was in the sender field. The trouble is > that your name was not there and I have no clue who is cyndis@kapsi.fi. > > > Best regards, > Krzysztof I see, that makes sense. Looks like when I did the above From field change I must have messed up my configuration somehow since it looks like older patches I've sent do have the full name. Thanks, I'll try to fix it for next version. Mikko
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index bd4c3086a2da..6e4e5cc75631 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -38,6 +38,8 @@ * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ @@ -132,6 +134,8 @@ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA234_CLK_VIC 167U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index e3b0e9da295d..73fdd18523a9 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -26,6 +26,8 @@ #define TEGRA234_SID_PCIE8 0x09 #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_VIC 0x34 /* * memory client IDs @@ -33,6 +35,7 @@ /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ @@ -65,6 +68,8 @@ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index f610eee9bce8..c3f7e380d2c6 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -18,5 +18,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_VIC 29U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 547ca3b60caa..1971400bf360 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -44,6 +44,7 @@ #define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_VIC 113U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U